View HD66776_951417.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HD66776
Low Temperature poly-silicon TFT Panel 256-channel Source Driver with Internal RAM for 262,144-color display
REJxxxxxxx-xxxxZ Rev.1.11 Oct.02.2003
Index Description ......................................................................................................... 6 Features ......................................................................................................... 7
Block Diagram................................................................................................... 8 Pin Functions..................................................................................................... 9 PAD Arrangement ............................................................................................ 14 Pad Coordinate.................................................................................................. 15 Bump Arrangement .......................................................................................... 18 Pin connecting resistance recommended value .............................................. 19 Block Function Descriptions ............................................................................ 20
System interface .................................................................................................................. 20 External Display Interface (RGB-I/F, VSYNC-I/F)............................................................ 21 Bit Operations...................................................................................................................... 21 Address Counter (AC) ......................................................................................................... 21 Graphics RAM (GRAM) ..................................................................................................... 21 Grayscale Voltage Generation Circuit................................................................................. 22 Timing Generator ................................................................................................................ 22 Oscillation Circuit (OSC) .................................................................................................... 22 Liquid Crystal Display Driver Circuit ................................................................................. 22 Interface with Power supply IC ........................................................................................... 22
GRAM Address Map ........................................................................................ 23
Relation between GRAM Addresses and Screen Position (SS = "0")................................. 23 Relation between GRAM data and Display contents (SS = "0")......................................... 24 Relation between GRAM Addresses and Screen Position (SS = "1")................................. 27 Relation between GRAM data and Display contents (SS = "1")......................................... 28
Rev.1.11, Oct.02.2003, page 1 of 175
www..com
www..com
www..com
HD66776
Instructions ........................................................................................................ 31
Outline ................................................................................................................................. 31 Instruction Description ........................................................................................................ 33 General Settings................................................................................................................... 33 Index.................................................................................................................................... 33 Start Oscillation (R000h)..................................................................................................... 33 Driver Output Conrol (R001h) ............................................................................................ 33 LCD-Driving-Waveform Control (R002h).......................................................................... 34 Entry Mode (R003h)............................................................................................................ 35 Display Control (1) (R007h)................................................................................................ 39 Display Control 2 (R008h) .................................................................................................. 42 Instruction for setting BP/FP ............................................................................................... 42 Gate Driver Interface Control (R00Ah)............................................................................... 43 External Display Interface Control 1) (R00Ch)................................................................... 45 Frame Cycle Control (1) (R00Dh)....................................................................................... 48 Formula for the frame frequency ......................................................................................... 48 External Display Interface Control (2) (R00Eh).................................................................. 49 External Display Interface Control (3) (R00Fh).................................................................. 50 LTPS Interface Control (1) (R010h).................................................................................... 51 LTPS Interface Control (2) (R011h).................................................................................... 52 LTPS Interface Control (3) (R012h).................................................................................... 53 LTPS Interface Control (4) (R013h).................................................................................... 54 LTPS Interface Control (5) (R014h).................................................................................... 55 LTPS Interface Control (6) (R015h).................................................................................... 56 LTPS Interface Control (7) (R016h).................................................................................... 57 LTPS Interface Control (8) (R017h).................................................................................... 58 LTPS Interface Control (9) (R018h).................................................................................... 59 LTPS Interface Control (10) (R019h).................................................................................. 60 LPTS Interface Control (11) (R01Ah)................................................................................. 61 LTPS Interface Control (12) (R01Bh) ................................................................................. 62 Specification of LTPS panel control signal ......................................................................... 63 Power control system instruction......................................................................................... 64 Power Control 1 (R100h) .................................................................................................... 64 Power Control 2 (R101h) .................................................................................................... 65 Power Control 3 (R102h) .................................................................................................... 66 Power Control 4 (R103h) .................................................................................................... 66 Power Control 5 (R104h) .................................................................................................... 66 Power Control 6 (R105h) .................................................................................................... 66 RAM Address Set (R200h) RAM Address Set (R201h) ..................................................... 67 Write Data to GRAM (R202h) ............................................................................................ 68 GRAM Data and LCD Output ............................................................................................. 72 RAM Access via RGB-I/F and System I/F.......................................................................... 74 Read Data from GRAM (R203h)......................................................................................... 75 RAM Write Data Mask (R203h) ......................................................................................... 78 RAM Write Data Mask (R204h) ......................................................................................... 78 Control (R300h to R309h) ................................................................................................ 79 Vertical Scroll Control (R400h) .......................................................................................... 80 Vertical Scroll Control (R401h) .......................................................................................... 80
Rev.1.11, Oct. 02.2003, page 2 of 175
HD66776 1st-screen driving position (1) (R402h)................................................................................ 81 1st-screen driving position (2) (R403h)................................................................................ 81 2nd-screen driving position (1) (R404h)............................................................................... 81 2nd-screen driving position (2) (R405h)............................................................................... 81 Horizontal RAM address position (R406h) ......................................................................... 82 Vertical RAM address position (R407h) ............................................................................. 82 Horizontal RAM address position (R408h) ......................................................................... 82 Vertical RAM address position (R409h) ............................................................................. 82
Instruction List.................................................................................................. 83 Reset Function ................................................................................................... 84
Instruction set initialization ................................................................................................. 84 GRAM Data Initialization ................................................................................................... 84 Output Pin Initialization ...................................................................................................... 84
Interface Specifications..................................................................................... 85 System Interface................................................................................................ 87
80-system 18-bit bus interface............................................................................................. 88 80-system 16-bit bus interface............................................................................................. 89 80-system 9-bit bus interface............................................................................................... 90 80-system 8-bit bus interface............................................................................................... 92 Serial clock synchronized interface (SPI)............................................................................ 95 Data format for serial interface ............................................................................................ 96 VSYNC Interface ................................................................................................................ 99
External Display Interface ............................................................................... 103
RGB interface ...................................................................................................................... 103 VLD and ENABLE signals ................................................................................................. 104 RGB interface timing........................................................................................................... 105 6-bit RGB interface timing .................................................................................................. 106 Moving picture display ........................................................................................................ 107 6-bit RGB interface ............................................................................................................. 109 16-bit RGB interface ........................................................................................................... 111 18-bit RGB interface ........................................................................................................... 112 Usage on external display interface ..................................................................................... 113 Writing RAM data from system I/F during displaying RGB I/F ......................................... 114
High-Speed Burst RAM Write Function ........................................................ 115
High-Speed RAM Write in the Window Address ............................................................... 117
Window Address Function ............................................................................... 118 Graphics Operation Function .......................................................................... 119
Write-data Mask Function ................................................................................................... 120 Graphics Operation Processing............................................................................................ 121
Rev.1.11, Oct. 02.2003, page 3 of 175
HD66776
-Correction Function....................................................................................... 122
Configuration of Grayscale Amplifier ................................................................................. 123 -Correction Registers ......................................................................................................... 125 Ladder resistors and 8 to 1 selector ..................................................................................... 126 Relation between RAM Data and Output level ................................................................... 132
8-Color Display Mode....................................................................................... 133 Example of System Configuration of TFT display ........................................ 138 Example of Chip set connecting....................................................................... 139 Instruction Setting Flow ................................................................................... 140 Oscillation circuit .............................................................................................. 149 n-raster-row Reversed AC Drive..................................................................... 150 AC Drive Timing............................................................................................... 151 Frame Frequency Adjusting Function............................................................ 152
Relationship between LCD Drive Duty and Frame Frequency ........................................... 152 Example of Calculation ....................................................................................................... 152
Screen-division Driving Function .................................................................... 153 Restrictions on the 1st/2nd Screen Driving Position Register Settings........... 154 Absolute Maximum Ratings............................................................................. 155 DC Characteristics (Vcc= 2.2 to 3.3V, Ta = -40 to +85oC*1).......................... 156 AC Characteristic (Vcc =2.2 to 3.3V, Ta = -40oC to +85oC )......................... 157
80-system Bus Interface Timing Characteristics (1)............................................................ 157 80-system Bus Interface Timing Characteristics (2)............................................................ 159 Clock Synchronized Serial Interface Timing Characteristics .............................................. 160 Reset Timing Characteristics (Vcc = 2.2 to 3.3V)............................................................... 160 RGB interface timing characteristic..................................................................................... 161 LCD driver output characteristic ......................................................................................... 162
Electrical Characteristics notes ....................................................................... 163 80-system Bus Operation.................................................................................. 166 Clock Synchronized Serial Interface Operation ............................................ 167 Reset Operation................................................................................................. 167
Rev.1.11, Oct. 02.2003, page 4 of 175
HD66776
RGB I/F Operation ........................................................................................... 168 LCD Driver Output Character ........................................................................ 168
Rev.1.11, Oct. 02.2003, page 5 of 175
HD66776
Description
The HD66776, a 256-channel source driver LSI, is used in combination with the HD667P20 power-supply IC to display 256 RGB-by-320-dot graphics on TFT color LCD displays in 262,144 colors. As well as the HD6766 is capable, in conjunction with the HD667P20 (power-supply IC), of outputting the signals for the control of low-temperature poly-silicon TFTs. The HD66776's bit-operation functions, 8/9/16/18-bit high-speed bus interface, and high-speed RAM-write functions enable the efficient transfer of data and the high-speed rewriting of data in the graphics RAM. The HD66776's 6/16/18-bit RGB interface (VSYNC, HSYNC, DOTCLK, ENABLE, and PD 17 to 0) and VSYNC interface (system interface + VSYNC) provide interfaces for use with animated displays. These interfaces provide a window-addressing function that facilitates the construction of a display in any area of the screen and allows the simultaneous display of animated images and the contents of internal RAM without concern for the static image areas. The HD66776 and HD667P20 have various functions for reducing the power consumption of a LCD system. The HD66776 features low-voltage operation (2.2 V min.) and an internal RAM from which it is able to drive a maximum of 256RGB-by-320-dot color images. HD66776 has voltage-followers to generate the LCD-driving voltage. Since the HD66776 incorporates a circuit that interfaces with the HD667P20, it is capable of setting instructions for the HD667P20. The device supports functions such as the eight-color display function and standby and sleep modes that allow precise power control by software. This LSI is suitable for any medium-sized or small portable product that is battery driven and requires a long battery life, such as digital cellular phones that support a WWW browser and small PDAs.
Rev.1.11, Oct. 02.2003, page 6 of 175
HD66776
Features
* 256RGB x 320-dot graphics display LCD controller/driver for 262,144 TFT colors (when used with the HD6677P20) * Control signals for the low-temperature poly-silicon TFT-panel compatible gate driver (HD66776 + HD667P20) * System interfaces 8-/9-/16-/18-bit high-speed bus interface Serial peripheral interface (SPI) * Interfaces for use with animated displays 6-/16-/18-bit RGB-I/F (VSYNC, HSYNC, DOTCLK, ENABLE, and PD 17 to 0) VSYNC-I/F (system I/F + VSYNC) * High-speed burst-RAM write function * A window-addressing function allows writing to the set of addresses in RAM that corresponds to a window's shape. The interfaces for animated displays facilitate the placing of animated pictures in any area of the screen. Selective transmission to the animated-display area reduces the amount of data transmitted. The contents of internal RAM may be displayed at the same time as the animated display. * Bit-operations for graphics processing: Write data mask function in bit units * Various functions for controlling color displays: * Simultaneous availability of 262,144 colors (-correction function) * Vertical scrolling in raster-row units * Features for low-power operation include: Vcc = 2.2 to 3.3 V (low-voltage range) DDVDH = 4.0 to 5.9 V (liquid-crystal driving voltage) Power-save functions such as the standby and sleep modes Partial LCD drive that displays two sub-screens in any position Maximum 12-times step-up circuit for the liquid-crystal driving voltage (HD667P20) Voltage followers to decrease the flow of direct current in the LCD drive's bleeder-resistors * Built-in circuit for interfacing with the HD6677P20 gate-driver/power-supply IC * Maximum 256RGB-by-320-dot display in combination with the HD6677P20 gate-driver/power-supply IC * 184,320 bytes of internal RAM * 256-output liquid-crystal display driver * n-raster-row AC liquid-crystal drive (can be set to a different polarity each line) * Internal oscillation and hardware reset * Reversible direction for the feeding of signals from RAM to the source driver.
Rev.1.11, Oct. 02.2003, page 7 of 175
HD66776
Block Diagram
ENABLE VSYNC HSYNC DOTCLK PD0 to 17
OSC1 OSC2
Vcc Index Register (IR) Control Register (CR)
18 External Display Interface
VSYNC, HSYNC, DCLK, ENABLE PD17 to 0
CPG
OSC3 FLM SFTCLK1 SFTCLK2 CLA CLB CLC DISPTMG M EQ DCCLK
18
IM3-1, IM0/ID CS* VLD RS WR*/SCL RD* DB0/SDI, DB1/SD0, to DB17 18
11
16 Address Counter (AC)
System Interface 18bit 16 bit 9bit 8bit Serial Peripheral (SPI) 16
Timing generator 18 Bit Operation
17 18 Read data latch
18
18 GCS* GCL GDA RESET01 RESET02 RESET* TEST VDDTEST Vci VDD1 VDD2 TS0 TS1 TS2 TS3 COM0P COM0M COM1P COM1M Power supply IC Interface (Serial)
Write data latch
LCD driving circuit
Graphic RAM (GRAM) 184,320 bytes
S1 to S256
M A/C circuit
Latch circuit
Latch circuit
Latch circuit
Gamma adjusting circuit
Grayscale voltage generator
Regulator
V0-63
VTEST
Rev.1.11, Oct. 02.2003, page 8 of 175
VREF
VRTEST
VM0N
PM0N
VGS DDVDH VDH GND
V0P, V0N, V63P, V63N
Vcom
HD66776
Pin Functions
Signal IM3-1, IM0/ID Number of pins 4 I/O I Connected to GND or Vcc Functions Settings select the MPU-interface mode as listed below. IM3 GND GND GND GND GND GND Vcc Vcc Vcc Vcc Vcc IM2 GND GND GND GND Vcc Vcc GND GND GND GND Vcc IM1 GND GND Vcc Vcc GND Vcc GND GND Vcc Vcc * IM0/ID MPU interface DB pin mode GND Vcc GND Vcc ID * GND Vcc Vcc Vcc *
Setting inhibited Setting inhibited
80-system 16-bit 80-system 8-bit Serial Peripheral Interface Setting inhibited Setting inhibited Setting inhibited 80-system 18-bit 80-system 9-bit Setting inhibited
FB17-10, 8-1 DB17-10 DB1-0

DB17-0 FB17-9
When the serial interface is selected, the iM0 pin is used to set the ID code for the device. CS* 1 I MPU Selects the HD66776: Low: the HD66776 is selected and is accessible. High:HD66776 is not selected and inaccessible Must be fixed to the GND level when not in use. Indicates whether or not the data is valid when writing to the RAM. Low: Valid (writing of data to RAM) High: Invalid (no writing of data to RAM). The RAM address will be updated whether VLD is high or low. Must be fixed to the GND level when no in use. This signal remains available when an external display interface is in use. Polarity of VLD signal is inverted by the setting of VPL register. VPL CS VLD RAM write RAM address 0 0 0 Valid Updated 0 0 1 Invalid Updated 0 1 * Invalid Held 0 0 0 Invalid Updated 0 0 1 Valid Updated 0 1 * Invalid Held Selects the register. Low: Index High: Control Fix to the "Vcc" or "GND" level while using SPI.
VLD
1
I
MPU
RS
1
I
MPU
Rev.1.11, Oct. 02.2003, page 9 of 175
HD66776
Signal WR*/SCL Number of pins 1 I/O I Connected to MPU Functions For an 80-system bus interface, serves as a write strobe signal. Data is written on this signal's low level. For a synchronous clock interface, serves as the synchronous clock signal. RD* 1 I MPU For an 80-system bus interface, serves as a read-strobe signal. Data is read on this signal's low level. Fix to the "Vcc" or "GND" level while using SPI. 18-bit bi-directional data bus. 8-bit interface: DB17-DB10 9-bit interface: DB17-DB9 16-bit interface: DB17-DB10 and DB8-DB1 18-bit interface: DB17-DB0 Unused pins must be fixed to the Vcc or GND level. Serves as the serial data input pin (SDI) of a clocksynchronous serial interface. The input level is read on the rising edge of the SCL signal. DB1/SD0 1 I/O MPU 18-bit bi-directional data bus. 8-bit interface: DB17-DB10 9-bit interface: DB17-DB9 16-bit interface: DB17-DB10 and 8 to 1 18-bit interface: DB17-DB0 Unused pins must be fixed to the Vcc or GND level. Serves as the serial data output pin (SDO) of a clocksynchronous serial interface. Output is from the falling edge of the SCL signal. 18-bit bi-directional data bus. 8-bit bus: DB17-DB10 9-bit bus: DB17-DB9 16-bit bus: DB17-DB10 and 8 to 1 18-bit bus: DB17-DB0 Unused pins must be fixed to the Vcc or GND level. Indicates whether or not RAM data is valid when the RGB interface is in use. Low: Selected (access enabled) High: Not selected (access disabled) Must be fixed to the Vcc or GND level when not in use. Polarity of ENABLE signal is inverted by the setting of EPL register. EPL ENABLE LVD RAM Write RAM Address 0 0 0 1 1 1 0 0 1 0 1 1 0 1 * * 0 1 Valid Invalid Invalid Invalid Valid Invalid Updated Updated Held Held Updated Updated
DB0/SD1
1
I/O
MPU
DB2-DB17
16
I/O
MPU
ENABLE
1
I
MPU
Rev.1.11, Oct. 02.2003, page 10 of 175
HD66776
Signal VSYNC Number of pins 1 I/O I Connected to MPU Functions Frame synchronization signal. Polarity is inverted by the setting of VSPL register. VSPL 0 1 HSYNC 1 I MPU VSYNC Low active High active Unused Vcc fixed GND fixed
Raster-row synchronization signal. Polarity is inverted by the setting of HSPL register. HSPL 0 1 HSYNC Low active High active Unused Vcc fixed GND fixed
DOTCLK
1
I
MPU
Dot-clock signal. Polarity is inverted by the setting of DPL signal. DPL 0 1 DPTCLK Data reading at low level Data reading at high level Unused Vcc fixed GND fixed
PD0-PD17
18
I
MPU
Serves as 18-bit bus for RGB data. 6-bit interface: DB17 to 12 16-bit interface: DB17 to 13 and DB11 to 1 18-bit interface: DB17 to 0 Must be fixed unused pins to the Vcc or GND level.
S1-S256
256
O
LCD
Outputs voltages for supply to the LCD. The SS bit can change the direction with which segment signals are obtained from RAM. For example, if SS = 0, the data at RAM address "00000" is output on S1. If SS = 1, it is output on S256. Output for the frame-start pulse. Gate shift clock for LTPS. Outputs 2-laster-row pulse. Gate shift clock for LTPS. Outputs 2-laster-row pulse. Signal for control of , , switching. Signal for control of , , switching. Signal for control of , , switching.
FLM1,2 SFTCLK11 SFTCLK12 SFTCLK21 SFTCLK22 CLA1 CLA2 CLB1 CLB2 CLC1 CLC2
2 2 2 2 2 2
O O O O O O
HD667P20 HD667P20 HD667P20 HD667P20 HD67P20 HD667P20
Rev.1.11, Oct. 02.2003, page 11 of 175
HD66776
Signal DISPTMG1 DISPTMG2 M1 M2 EQ1 EQ2 Number of pins 2 2 2 I/O O O O Connected to HD667P20 HD667P20 HD667P20 Functions Gate-control signal for LTPS. Output for the AC-cycle pulse. Indicates setting of the Vcom output to its highimpedance state during transitions of Vcom when Vcom is being AC-cycled. Low: VcomH or VcomL is being output on the Vcom pin. High: Vcom pin is in high-impedance state. Outputs the clock signal for the step-up circuit. Clock signal for the serial transfer of register setting to the power-supply IC. Data is output on the falling edges of this signal. Data signal for the serial transfer of register setting to the power-supply IC. Chip-select signal for the HD667P20. Low: the HD667P20 is selected and can receive serially transferred data. High: the HD667P20is not selected and cannot receive serially transferred data. Input for the LCD-driving voltage, which can be provided by the HD667P20. DDVDH: from +4.0 to 5.9 V Reference level for grayscale voltage generation circuit, which can be provided by the HD667P20. Signal for the equalizer functions. All LCD outputs (S1-S256) are shorted to the Vcom level (high-impedance). When VcomL is lower than 0 V, this signal should not be connected. VCC: + 2.2 V to + 3.3 V; GND (logic): 0 V Ground for analog. AGND:0V For connecting an external resistor for R-C oscillation. Test pin. Must not be connected. Reset pin. Setting either pin low initializes the LSI. Must be reset after power is supplied. Input data through RESET1 or RESET2. Unused pins should not be connected. Outputs the same level of voltage of same polarity with RESET*. HD66776 and HD667P20 can be controlled simultaneously by connecting to HD667P20. Outputs the internal Vcc level, shorting this pin sets the adjacent input pin to the GND level. Outputs the internal GND level, shorting this pin sets the adjacent input pin to the GND level.
DCCLK1 DCCLK2 GCL1 GCL2 GDA1 GDA2 GCS1* GCS2*
2 2
O O
HD667P20
2 2
O O
DDVDH VDH Vcom
1 1 1
I I I HD667P20 HD67P20
Vcc, GND AGND OSC1 OSC2 OSC3 RESET*
2 2 2 1 1
-- -- I/O O I
Power supply Power supply Resistor for the oscillator Open MPU or external R-C circuit HD667P20
RESET01 RESET02 VccDUM GNDDUM
2
O
O O
Input pins Input pins
Rev.1.11, Oct. 02.2003, page 12 of 175
HD66776
Signal DUMMY1 to DUMMY2, DUMMY29 to Dummy33 DUMMY 27 DUMMY 28 DYUMM34 DUMMY 35 DUMMY3 to DUMMY26, DUMMY36 to DUMMY 59 TEST V0P, V63P 1 2 I I/O GND Capacitor for stabilization Test pin. Must be fixed to GND level. Internal op-amp outputs that produce a positive polarity (V0 can be used for both polarities) when the internal opamp is on (SAP2-0 ="001", "010", "011", "100", or "101"). For connection to capacitors for stabilization. Internal op-amp outputs that produce a negative polarity when the internal op-amp is on (SAP2-0 ="001", "010", "011", "100", or "101"). For connection to capacitors for stabilization. Reference level for the grayscale-voltage generation circuit. For connection to a variable resistor that adjusts the source-driver level for a panel. Test pin. Must be disconnected. Test pin. Must be disconnected. Test pin. Must be disconnected. Vci: +2.5V to 3.3V Internal logic power supply. Do not connect to other than capacitor for stabilization or VDD2. Internal logic power supply. Do not connect to other than capacitor for stabilization or VDD1. Test pin. Must be disconnected. Test pin. Must be disconnected. 48 -- Open NC pin. It is possible to use these pins as transfer points for the signal cable when COG mounting. Number of pins 7 I/O -- Connected to Open Functions Dummy pad. Must be open.
4
--
Open
Test pin. Must be Open.
V0N, V63N
2
I/O
Capacitor for stabilization
VGS
1
I
GND or External resistor Open Open Open Power supply VDD2, Capacitor for stabilization VDD1, Capacitor for stabilization Open Open
VTEST PMON VMON VCI VDD1
1 1 1 1 1
O O O -- I/O
VDD2
1
I/O
TS0-TS3 COM0P, COM0M, COM1P, COM1M VDDTEST VREF VRTEST
3 4 I/O
1 1 1
I O O
GND Open Open
Test pin. Must be fixed to "GND" level. Test pin. Must be disconnected. Test pin. Must be disconnected.
Rev.1.11, Oct. 02.2003, page 13 of 175
HD66776
PAD Arrangement
DUMMY59 DUMMY36
NO.476
Dummy 24
NO.453
NO.1 NO.2 DUMMY1 RESETO1 CLC1 CLB1 CLA1 FLM1 SFTCLK21 SFTCLK11 M1 EQ1 DISPTMG1 GDA1 GCS1* GCL1 DCCLK1 RESET* DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1/SDO DB0/SDI RD* WR*/SCL RS CS* VLD GNDDUM1 VSYNC HSYNC DOTCLK ENABLE PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Vcc Vcc Vcc Vcc Vcc Vcc Vci Vci Vci Vci Vci Vci Vci Vci VREF VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 GND GND GND GND GND GND GND GND GND GND GND GND GND AGND AGND AGND AGND AGND AGND AGND AGND VRTEST VDDTEST V0P V0N V63P V63N VGS VDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH PMON VMON VTEST Vcom Vcom COM1M TS3 TS2 COM1P COM0M TS1 TS0 COM0P OSC1 OSC2 OSC3 VccDUM1 IM0/ID IM1 IM2 IM3 GNDDUM2 TEST DCCLK2 GCL2 GCS2* GDA2 DISPTMG2 EQ2 M2 SFTCLK12 SFTCLK22 FLM2 CLA2 CLB2 CLC2 RESETO2 DUMMY2
NO.452 DUMMY35 NO.451 S1 S2 S3 S4
Chip size: 13.89 x 2.94mm Chip thickness: 400 m (typ.) Pad coordinate: Pad center Coordinate original: Chip center Au bump size (1) 80m x 80m DUMMY1(No.1) to DUMMY2(No.163) DUMMY27(No.188) to DUMMY35(No.452) (2) 56m x 90m RESET01 (No.2) to RESET02 (NO.162) (3) 80m x 76m DUMMY3(No.164) to DUMMY26(No.187) DUMMY36 (No.453) to DUMMY59(No.476) (4) 35m x 70m S1(No.451) to S128 (No.324) S129 (No.316) to S256(No.189) (5) 76m x 80m DUMMY28(No.317) to DUMMY34(No.323) Au bump chip: Refer to pad coordinate Au bump height: 15m (typ.) Numbers in a diagram indicate numbers in PAD coordinate. Alignment mark (1) PAD coordinate: Two places (1-a) Coordinate (X,Y) = (-6636.00, -832.50) (1-b) Coordinate (X,Y) = (6636.00, -832.50)
100m 50
30
(3-a) (1-a)
(2-a)
Type Code: HD667B76
100m
HD667B76 Laced Top View
S125 S126 S127 S128 DUMMY34 DUMMY33
NO.324
50
40
30
NO.323
Dummy 7
DUMMY29 DUMMY28 S129 S130 S131 S132
30
40
30
NO.317 NO.316
(2) Arrangement coordinate (2-a) Coordinate (X, Y) = (-6686.00, -692.50)
50m
(2-b) Coordinate (X, Y) = (6686.00, -692.50)
20
50m
(3) Arrangement coordinate (3-a) Coordinate (X, Y) = (-6686.00, -972.50)
5 10 25 25 10 5
10 5 80m 70m
70m 80m
(3-b) Coordinate (X, Y) = (6686.00, -972.50)
10 25 25 10
25
25
10
5 10
25
25
10
DUMMY3
DUMMY26
Rev.1.11, Oct. 02.2003, page 14 of 175
70m
NO.162 NO.163
(3-a) (1-a)
(2-a)
S253 S254 S255 S256 DUMMY27 NO.189
70m
NO.188
Dummy 24
NO.164
NO.187
HD66776
Pad Coordinate
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pad Name DUMMY1 RESETO1 CLC1 CLB1 CLA1 FLM1 SFTCLK21 SFTCLK11 M1 EQ1 DISPTMG1 GDA1 GCS1* GCL1 DCCLK1 RESET* DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1/SDO DB0/SDI RD* WR*/SCL RS CS* VLD GNDDUM1 VSYNC HSYNC DOTCLK ENABLE PD17 PD16 PD15 PD14 PD13 PD12 X -6827.0 -6645.0 -6565.0 -6485.0 -6405.0 -6325.0 -6245.0 -6165.0 -6085.0 -6005.0 -5925.0 -5845.0 -5765.0 -5685.0 -5605.0 -5525.0 -5415.0 -5335.0 -5255.0 -5175.0 -5095.0 -5015.0 -4935.0 -4855.0 -4775.0 -4695.0 -4615.0 -4535.0 -4455.0 -4375.0 -4295.0 -4215.0 -4135.0 -4055.0 -3975.0 -3895.0 -3815.0 -3735.0 -3655.0 -3575.0 -3495.0 -3415.0 -3335.0 -3255.0 -3175.0 -3095.0 -3015.0 -2935.0 -2855.0 -2775.0 Y -1344.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pad Name PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 VCC VCC VCC VCC VCC VCC VCI VCI VCI VCI VCI VCI VCI VCI VREF VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 GND GND GND GND GND GND GND GND GND GND X -2695.0 -2615.0 -2535.0 -2455.0 -2375.0 -2295.0 -2215.0 -2135.0 -2055.0 -1975.0 -1895.0 -1815.0 -1665.0 -1585.0 -1505.0 -1425.0 -1345.0 -1265.0 -1185.0 -1105.0 -1025.0 -945.0 -865.0 -785.0 -705.0 -625.0 -525.0 -425.0 -345.0 -265.0 -185.0 -105.0 -25.0 55.0 135.0 215.0 295.0 375.0 455.0 535.0 635.0 715.0 795.0 875.0 955.0 1035.0 1115.0 1195.0 1275.0 1355.0 Y -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Pad Name GND GND GND AGND AGND AGND AGND AGND AGND AGND AGND VRTEST VDDTEST V0P V0N V63P V63N VGS VDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH PMON VMON VTEST VCOM VCOM COM1M TS3 TS2 COM1P COM0M TS1 TS0 COM0P OSC1 OSC2 OSC3 VCCDUM1 IM0/ID IM1 IM2 IM3 GNDDUM2 TEST DCCLK2 GCL2 X 1435.0 1515.0 1595.0 1675.0 1755.0 1835.0 1915.0 1995.0 2075.0 2155.0 2235.0 2355.0 2495.0 2675.0 2755.0 2835.0 2915.0 2995.0 3075.0 3175.0 3255.0 3335.0 3415.0 3495.0 3575.0 3675.0 3755.0 3835.0 3915.0 3995.0 4095.0 4175.0 4255.0 4335.0 4415.0 4495.0 4575.0 4655.0 4805.0 4885.0 4965.0 5045.0 5125.0 5205.0 5285.0 5365.0 5445.0 5525.0 5605.0 5685.0 Y -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Pad Name GCS2* GDA2 DISPTMG2 EQ2 M2 SFTCLK12 SFTCLK22 FLM2 CLA2 CLB2 CLC2 RESETO2 DUMMY2 DUMMY3 DUMMY4 DUMMY5 DUMMY6 DUMMY7 DUMMY8 DUMMY9 DUMMY10 DUMMY11 DUMMY12 DUMMY13 DUMMY14 DUMMY15 DUMMY16 DUMMY17 DUMMY18 DUMMY19 DUMMY20 DUMMY21 DUMMY22 DUMMY23 DUMMY24 DUMMY25 DUMMY26 DUMMY27 S256 S255 S254 S253 S252 S251 S250 S249 S248 S247 S246 S245 X 5765.0 5845.0 5925.0 6005.0 6085.0 6165.0 6245.0 6325.0 6405.0 6485.0 6565.0 6645.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6827.0 6521.4 6473.2 6425.0 6376.8 6328.6 6280.4 6232.2 6184.0 6135.8 6087.6 6039.4 5991.2 Y -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1339.3 -1344.3 -1150.0 -1050.0 -950.0 -850.0 -750.0 -650.0 -550.0 -450.0 -350.0 -250.0 -150.0 -50.0 50.0 150.0 250.0 350.0 450.0 550.0 650.0 750.0 850.0 950.0 1050.0 1150.0 1344.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6
Rev.1.11, Oct. 02.2003, page 15 of 175
HD66776
No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 Pad Name S244 S243 S242 S241 S240 S239 S238 S237 S236 S235 S234 S233 S232 S231 S230 S229 S228 S227 S226 S225 S224 S223 S222 S221 S220 S219 S218 S217 S216 S215 S214 S213 S212 S211 S210 S209 S208 S207 S206 S205 S204 S203 S202 S201 S200 S199 S198 S197 S196 S195 X 5943.0 5894.8 5846.6 5798.4 5750.2 5702.0 5653.8 5605.6 5557.4 5509.2 5461.0 5412.8 5364.6 5316.4 5268.2 5220.0 5171.8 5123.6 5075.4 5027.2 4979.0 4930.8 4882.6 4834.4 4786.2 4738.0 4689.8 4641.6 4593.4 4545.2 4497.0 4448.8 4400.6 4352.4 4304.2 4256.0 4207.8 4159.6 4111.4 4063.2 4015.0 3966.8 3918.6 3870.4 3822.2 3774.0 3725.8 3677.6 3629.4 3581.2 Y 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 No. 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 Pad Name S194 S193 S192 S191 S190 S189 S188 S187 S186 S185 S184 S183 S182 S181 S180 S179 S178 S177 S176 S175 S174 S173 S172 S171 S170 S169 S168 S167 S166 S165 S164 S163 S162 S161 S160 S159 S158 S157 S156 S155 S154 S153 S152 S151 S150 S149 S148 S147 S146 S145 X 3533.0 3484.8 3436.6 3388.4 3340.2 3292.0 3243.8 3195.6 3147.4 3099.2 3051.0 3002.8 2954.6 2906.4 2858.2 2810.0 2761.8 2713.6 2665.4 2617.2 2569.0 2520.8 2472.6 2424.4 2376.2 2328.0 2279.8 2231.6 2183.4 2135.2 2087.0 2038.8 1990.6 1942.4 1894.2 1846.0 1797.8 1749.6 1701.4 1653.2 1605.0 1556.8 1508.6 1460.4 1412.2 1364.0 1315.8 1267.6 1219.4 1171.2 Y 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 No. 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 Pad Name S144 S143 S142 S141 S140 S139 S138 S137 S136 S135 S134 S133 S132 S131 S130 S129 DUMMY28 DUMMY29 DUMMY30 DUMMY31 DUMMY32 DUMMY33 DUMMY34 S128 S127 S126 S125 S124 S123 S122 S121 S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 X 1123.0 1074.8 1026.6 978.4 930.2 882.0 833.8 785.6 737.4 689.2 641.0 592.8 544.6 496.4 448.2 400.0 300.0 200.0 100.0 0.0 -100.0 -200.0 -300.0 -400.0 -448.2 -496.4 -544.6 -592.8 -641.0 -689.2 -737.4 -785.6 -833.8 -882.0 -930.2 -978.4 -1026.6 -1074.8 -1123.0 -1171.2 -1219.4 -1267.6 -1315.8 -1364.0 -1412.2 -1460.4 -1508.6 -1556.8 -1605.0 -1653.2 Y 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1344.6 1344.6 1344.6 1344.6 1344.6 1344.6 1344.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 No. 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 Pad Name S101 S100 S99 S98 S97 S96 S95 S94 S93 S92 S91 S90 S89 S88 S87 S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 X -1701.4 -1749.6 -1797.8 -1846.0 -1894.2 -1942.4 -1990.6 -2038.8 -2087.0 -2135.2 -2183.4 -2231.6 -2279.8 -2328.0 -2376.2 -2424.4 -2472.6 -2520.8 -2569.0 -2617.2 -2665.4 -2713.6 -2761.8 -2810.0 -2858.2 -2906.4 -2954.6 -3002.8 -3051.0 -3099.2 -3147.4 -3195.6 -3243.8 -3292.0 -3340.2 -3388.4 -3436.6 -3484.8 -3533.0 -3581.2 -3629.4 -3677.6 -3725.8 -3774.0 -3822.2 -3870.4 -3918.6 -3966.8 -4015.0 -4063.2 Y 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6
Rev.1.11, Oct. 02.2003, page 16 of 175
HD66776
No. 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 Pad Name S51 S50 S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 X -4111.4 -4159.6 -4207.8 -4256.0 -4304.2 -4352.4 -4400.6 -4448.8 -4497.0 -4545.2 -4593.4 -4641.6 -4689.8 -4738.0 -4786.2 -4834.4 -4882.6 -4930.8 -4979.0 -5027.2 -5075.4 -5123.6 -5171.8 -5220.0 -5268.2 -5316.4 -5364.6 -5412.8 -5461.0 -5509.2 -5557.4 -5605.6 -5653.8 -5702.0 -5750.2 -5798.4 -5846.6 -5894.8 -5943.0 -5991.2 -6039.4 -6087.6 -6135.8 -6184.0 -6232.2 -6280.4 -6328.6 -6376.8 -6425.0 -6473.2 Y 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 1249.6 1349.6 No. 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 Pad Name S1 DUMMY35 DUMMY36 DUMMY37 DUMMY38 DUMMY39 DUMMY40 DUMMY41 DUMMY42 DUMMY43 DUMMY44 DUMMY45 DUMMY46 DUMMY47 DUMMY48 DUMMY49 DUMMY50 DUMMY51 DUMMY52 DUMMY53 DUMMY54 DUMMY55 DUMMY56 DUMMY57 DUMMY58 DUMMY59 X -6521.4 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 -6827.0 Y 1249.6 1344.6 1150.0 1050.0 950.0 850.0 750.0 650.0 550.0 450.0 350.0 250.0 150.0 50.0 -50.0 -150.0 -250.0 -350.0 -450.0 -550.0 -650.0 -750.0 -850.0 -950.0 -1050.0 -1150.0
Rev.1.11, Oct. 02.2003, page 17 of 175
HD66776
Bump Arrangement
13 SI to 256 (Laced) 70
30
35
70 Unit: m
48 RESET01 to RESET02
80 24
90 Unit: m 56 56
DUMMY3 to 26, 28 to 34, 36 to 59 100
80 Unit: m 76 24 76
DUMMY1, 2, 27, 35
80
Unit: m 80
Rev.1.11, Oct. 02.2003, page 18 of 175
HD66776
Pin connecting resistance recommended value
DUMMY59 DUMMY36
OPEN 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100
DUMMY1 RESETO1 CLC1 CLB1 CLA1 FLM1 SFTCLK21 SFTCLK11 M1 EQ1 DISPTMG1 GDA1 GCS1* GCL1 DCCLK1 RESET* DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1/SDO DB0/SDI RD* WR*/SCL RS CS* VLD GNDDUM1 VSYNC HSYNC DOTCLK ENABLE PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Vcc Vcc Vcc Vcc Vcc Vcc Vci Vci Vci Vci Vci Vci Vci Vci VREF VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD1 VDD2 VDD2 GND GND GND GND GND GND GND GND GND GND GND GND GND AGND AGND AGND AGND AGND AGND AGND AGND VRTEST VDDTEST V0P V0N V63P V63N VGS VDH DDVDH DDVDH DDVDH DDVDH DDVDH DDVDH PMON VMON VTEST Vcom Vcom COM1M TS3 TS2 COM1P COM0M TS1 TS0 COM0P OSC1 OSC2 OSC3 VccDUM1 IM0/ID IM1 IM2 IM3 GNDDUM2 TEST DCCLK2 GCL2 GCS2* GDA2 DISPTMG2 EQ2 M2 SFTCLK12 SFTCLK22 FLM2 CLA2 CLB2 CLC2 RESETO2 DUMMY2
DUMMY26 DUMMY3
DUMMY35 S1 S2 S3 S4 Type Code: HD667B76
OPEN
1) When mounting HD66776 by COG, the resistance value that is loaded onto each pin must be lower than the value indicated in the figure. 2) Pins with the sign "OPEN" must be disconnected. 3) DUMMY3 to DUMMY26 and DUMMY36 to DUMMY59 are electrically Hi-z. They can be used as transfer points of signal wiring while mounting HD66776 by COG.
10
10
OPEN
HD667B76 Laced Top View
S125 S126 S127 S128 DUMMY34 DUMMY33
OPEN OPEN
5
DUMMY29 DUMMY28 S129 S130 S131 S132
OPEN OPEN
5
10
OPEN 100 100 100 100 100 100 100
10
OPEN OPEN OPEN 100 OPEN OPEN OPEN OPEN OPEN OPEN OPEN OPEN 100 100 OPEN 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 OPEN
S253 S254 S255 S256 DUMMY27 OPEN
Rev.1.11, Oct. 02.2003, page 19 of 175
HD66776
Block Function Descriptions
System interface The HD66776 has five high-speed system interfaces: an 80-system 18-bit/16-bit/9-bit/8-bit bus and a clocked serial peripheral (SPI: Serial Peripheral Interface) port. The interface mode is selected by the IM30 pins. The HD66776 has three registers: a 16-bit index register (IR), an 18-bit write-data register (WDR), and an 18-bit read-data register (RDR). The IR stores index information from the control registers and the GRAM. The WDR temporarily stores data to be written into control registers and the GRAM, and the RDR temporarily stores data read from the GRAM. Data written into the GRAM from the MPU is first written into the WDR and then is automatically written into the GRAM by internal operation. Data is read through the RDR when reading from the GRAM, and the first read data is invalid and the second and the following data are normal. Execution time for instruction excluding oscillation start is 0 clock cycle and instructions can be written in succession. Register Selection (8/9/16/18 Parallel interface)
80-system Bus WR* 0 1 0 1 RD* 1 0 1 0 RS 0 0 1 1 Operation Writes index to IR. Setting inhibited. Writes to control registers and GRAM through WDR. Reads data from GRAM through RDR.
Values of CS and VLD during RAM Write
VPL CS* 0 0 1 0 1 0 1 1 0 1 VLD 0 0 1 1 0 0 1 1 Operations Data is written to the GRAM. RAM address is updated. Data is not written to the GRAM. RAM address is not updated. Data is not written to the GRAM. RAM address is updated. Data is not written to the GRAM. RAM address is not updated. Data is not written to the GRAM, RAM address is updated. Data is not written to the GRAM. RAM address is not updated. Data is written to the GRAM. RAM address is updated. Data is not written to the GRAM. RAM address is not updated.
Note: The value of VLD only has a meaning for the RAM write instructions.
Rev.1.11, Oct. 02.2003, page 20 of 175
HD66776 Register selection (Serial peripheral interface)
Start bytes R/W-bit 0 1 0 1 RS-bit 0 0 1 1 Operations Writes an index into IR. Setting inhibited. Writes data to control registers and GRAM through WDR. Reads data from GRAM through RDR.
External Display Interface (RGB-I/F, VSYNC-I/F) The HD66776 incorporates RGB and VSYNC interfaces as external interfaces for the reproduction of animated displays. When the RGB-I/F is selected, the synchronization signals, which are VSYNC, HSYNC, and DOTCLK and are supplied from the external interfaces, are available for use in operating the display. The data for display (PD17-0) are written according to the values of the data enable signal (ENABLE) and data valid signal (VLD) in synchronization with the VSYNC, HSYNC, and DOTCLK signals. This allows flicker-free updating of the screen. When the VSYNC-I/F is selected, operations other than frame synchronization by the VSYNC signal are synchronized with the internal clock. The data for display is written to the GRAM via the system interface. There are some limitations on the timing and methods of writing to RAM. See the section on the external display interface. Switching from and to the system interface is done by instructions. The interface, therefore, can be selected according to whether the screen is displaying moving or still pictures. All data written via the RGB-I/F are written to the GRAM. Therefore, data is only transferred when the screen is updated, which reduces the amount of data transferred and the consumption of power when moving pictures are being displayed. Bit Operations The HD66772 is equipped with a write data mask function that selects and writes data into the GRAM. For details, see the section on the graphics operation functions. Address Counter (AC) The address counter (AC) assigns addresses to the GRAM. When an address set instruction is written into the IR, the address information is sent from the IR to the AC. After writing into the GRAM, the AC is automatically incremented by 1 (or decremented by 1). After reading from the data, the AC is not updated. A window address function allows for data to be written only to a window area specified by GRAM. Graphics RAM (GRAM) The graphics RAM (GRAM) has 18 bits/pixel and stores the bit-pattern data of 256 x 320 bytes.
Rev.1.11, Oct. 02.2003, page 21 of 175
HD66776 Grayscale Voltage Generation Circuit The grayscale voltage generation circuit generates LCD-driving voltages according to the grayscale data set in the -correction register. 262,144 colors are simultaneously available for display. For details, see the section on the -correction register. Timing Generator The timing generator generates timing signals for the operation of internal circuits such as the GRAM. The RAM read timing for display and internal operation timing by MPU access is generated separately to avoid interference with one another. The timing generator generates the interface signals (M, FLM, SFTCLK, SFTCLK2, CLA, CLB, CLC, EQ, DISPTMG, and DCCLK) for the power-supply IC. Oscillation Circuit (OSC) The HD66776 can provide R-C oscillation simply through the addition of an external oscillation-resistor between the OSC1 and OSC2 pins. The appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. Since R-C oscillation stops during the standby mode, current consumption can be reduced. For details, see the Oscillation Circuit section. Liquid Crystal Display Driver Circuit The liquid crystal display driver circuit consists of 256 source drivers (S1 to S256). The shift direction of 256-bit data can be changed by the SS bit by selecting an appropriate direction for the device mounting configuration. Interface with Power supply IC A serial interface circuit provides an interface with the HD667P20. When sending an instruction setting from the HD66776 to the HD667P20, a register setting value from within the HD66776 is transferred via the serial interface circuit. A transfer is started by setting a serial transfer enable in the HD66776. However, transfer to and reading from the HD6677P20 are not possible during standby. For details, see the Gate serial transfer to and from the gate driver.
Rev.1.11, Oct. 02.2003, page 22 of 175
HD66776
GRAM Address Map
Relation between GRAM Addresses and Screen Position (SS = "0")
S Pin/Display line Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 Line 13 Line 14 Line 15 Line 16 Line 17 Line 18 Line 19 Line 20
S1
PD 17 ----PD 0 PD 17
S2
----PD 0 PD 17
S3
----PD 0 PD 17
S4
----PD 0 PD 17
S5
----PD 0
.........
PD 17
S255
----PD 0
S256
PD PD ----0 17
"00000"H "00100"H "00200"H "00300"H "00400"H "00500"H "00600"H "00700"H "00800"H "00900"H "00A00"H "00B00"H "00C00"H "00D00"H "00E00"H "00F00"H "01000"H "01100"H "01200"H "01300"H
"00001"H "00101"H "00201"H "00301"H "00401"H "00501"H "00601"H "00701"H "00801"H "00901"H "00A01"H "00B01"H "00C01"H "00D01"H "00E01"H "00F01"H "01001"H "01101"H "01201"H "01301"H
"00002"H "00102"H "00202"H "00302"H "00402"H "00502"H "00602"H "00702"H "00802"H "00902"H "00A02"H "00B02"H "00C02"H "00D02"H "00E02"H "00F02"H "01002"H "01102"H "01202"H "01302"H
"00003"H "00103"H "00203"H "00303"H "00403"H "00503"H "00603"H "00703"H "00803"H "00903"H "00A03"H "00B03"H "00C03"H "00D03"H "00E03"H "00F03"H "01003"H "01103"H "01203"H "01303"H
"00004"H "00104"H "00204"H "00304"H "00404"H "00504"H "00604"H "00704"H "00804"H "00904"H "00A04"H "00B04"H "00C04"H "00D04"H "00E04"H "00F04"H "01004"H "01104"H "01204"H "01304"H
......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... .........
"000FE"H "001FE"H "002FE"H "003FE"H "004FE"H "005FE"H "006FE"H "007FE"H "008FE"H "009FE"H "00AFE"H "00BFE"H "00CFE"H "00DFE"H "00EFE"H "00FFE"H "010FE"H "011FE"H "012FE"H "013FE"H
"000FF"H "001FF"H "002FF"H "003FF"H "004FF"H "005FF"H "006FF"H "007FF"H "008FF"H "009FF"H "00AFF"H "00BFF"H "00CFF"H "00DFF"H "00EFF"H "00FFF"H "010FF"H "011FF"H "012FF"H "013FF"H
......
......
......
......
......
......
......
Line 319 Line 320
"13E00"H "13F00"H
"13E01"H "13F01"H
"13E02"H "13F02"H
"13E03"H "13F03"H
"13E04"H "13F04"H
"13EFE"H "13FFE"H
"13EFF"H "13FFF"H
Rev.1.11, Oct. 02.2003, page 23 of 175
......
HD66776 Relation between GRAM data and Display contents (SS = "0")
80-system 18-bit interface
GRAM Data DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB DB 8 7 DB 6 DB 5 DB DB 4 3 DB 2 DB 1 DB 0
RGB Arrangement Output Pins Output BGR= "0" order BGR= "1"
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Sn + 1
1 3
2 2
3 1
Note: n = lower eight bit of address (0 to 255)
80-system 16-bit interface
GRAM Data DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB DB 8 7 DB 6 DB 5 DB DB 4 3 DB 2 DB 1
RGB Arrangement Output Pins Output BGR= "0" order BGR= "1"
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Sn + 1
1 3
2 2
3 1
Note: n = lower eight bit of address (0 to 255)
80-system 9-bit interface
GRAM Data DB 17 DB 16
First transfer
DB 13 DB 12 DB 11 DB 10 DB DB DB 9 17 16
Second transfer
DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB 9
DB DB 15 14
RGB Arrangement Output Pins Output BGR= "0" order BGR= "1"
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Sn + 1
1 3
2 2
3 1
Note: n = lower eight bit of address (0 to 255)
80-system 8-bit interface (1) (two times transfer/pixel)
First transfer
GRAM Data DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16
Second transfer
DB DB 15 14 DB 13 DB 12 DB 11 DB 10
RGB Arrangement Output Pins Output BGR= "0" order BGR= "1"
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Sn + 1
1 3
2 2
3 1
Note: n = lower eight bit of address (0 to 255)
Rev.1.11, Oct. 02.2003, page 24 of 175
HD66776
80-system 8-bit interface (2) (three times transfer/pixel)
First tran sfer DB DB 11 10 Second tran sfer DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 Thi rd t ransfer DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10
GRA M Dat a
RGB Arra ng em ent Ou tput P ins Ou tput BG R= "0" orde r BG R= "1"
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Sn + 1 1 3 2 2 3 1 Note: n = lower eight bi t of ad dres s ( 0 to 25 5)
80-system 8-bit interface (3) (three times transfer/pixel)
First tran sfer GRA M Dat a DB DB DB DB DB DB 17 16 15 14 13 12 Second tran sfer DB DB DB DB DB DB 17 16 15 14 13 12 Thi rd t ransfer DB DB DB DB DB DB 17 16 15 14 13 12
RGB Arra ng em ent Ou tput P ins Ou tput BG R= "0" orde r BG R= "1"
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Sn + 1 1 3 2 2 3 1 Note: n = lower eight bi t of ad dres s ( 0 to 25 5)
SPI (two times transfer/pixel)
First tran sfer DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 Second tran sfer DB 15 DB 14 DB 13 DB 12 DB 11 DB 10
GRA M Dat a
RGB Arra ng em ent Ou tput P ins Ou tput BG R= "0" orde r BG R= "1"
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Sn + 1 1 3 2 2 3 1 Note: n = lower eight bi t of ad dres s ( 0 to 25 5)
Rev.1.11, Oct. 02.2003, page 25 of 175
HD66776
18-bit RGB interface
GRA M Dat a PD 17 PD 16 PD 15 PD 14 PD 13 PD 12 PD 11 PD 10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 PD 0
RGB Arra ng em ent Ou tput P ins Ou tput BG R = "0" orde r BG R = "1"
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Sn + 1 1 3 2 2 3 1
16-bit RGB interface
GRAM D ata PD 17 PD 16 PD 15 PD 14 PD 13 PD 11 PD 10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1
RGB Arra ng em ent Ou tput P ins Ou tput BG R = "0" orde r BG R = "1"
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Sn + 1 1 3 2 2 3 1
6-bit RGB interface
First transfer GRAM D ata PD 17 PD 16 PD 15 PD 14 PD 13 PD 12 PD 17 PD 16 Second transfer PD 15 PD 14 PD 13 PD 12 PD 17 PD 16 Third transfer PD 15 PD 14 PD 13 PD 12
RGB Arra ng em ent Ou tput P ins Ou tput BG R = "0" orde r BG R = "1"
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Sn + 1
Rev.1.11, Oct. 02.2003, page 26 of 175
HD66776 Relation between GRAM Addresses and Screen Position (SS = "1")
S Pin/Display line Line 1 Line 2 Line 3 Line 4 Line 5 Line 6 Line 7 Line 8 Line 9 Line 10 Line 11 Line 12 Line 13 Line 14 Line 15 Line 16 Line 17 Line 18 Line 19 Line 20
S1
PD 17 ----PD 0 PD 17
S2
----PD 0 PD 17
S3
----PD 0 PD 17
S4
----PD 0 PD 17
S5
----PD 0
.........
PD 17
S255
----PD 0
S256
PD PD ----0 17
"000FF"H "001FF"H "002FF"H "003FF"H "004FF"H "005FF"H "006FF"H "007FF"H "008FF"H "009FF"H "00AFF"H "00BFF"H "00CFF"H "00DFF"H "00EFF"H "00FFF"H "010FF"H "011FF"H "012FF"H "013FF"H
"000FE"H "001FE"H "002FE"H "003FE"H "004FE"H "005FE"H "006FE"H "007FE"H "008FE"H "009FE"H "00AFE"H "00BFE"H "00CFE"H "00DFE"H "00EFE"H "00FFE"H "010FE"H "011FE"H "012FE"H "013FE"H
"000FD"H "001FD"H "002FD"H "003FD"H "004FD"H "005FD"H "006FD"H "007FD"H "008FD"H "009FD"H "00AFD"H "00BFD"H "00CFD"H "00DFD"H "00EFD"H "00FFD"H "010FD"H "011FD"H "012FD"H "013FD"H
"000FC"H "001FC"H "002FC"H "003FC"H "004FC"H "005FC"H "006FC"H "007FC"H "008FC"H "009FC"H "00AFC"H "00BFC"H "00CFC"H "00DFC"H "00EFC"H "00FFC"H "010FC"H "011FC"H "012FC"H "013FC"H
"000EB"H "001EB"H "002EB"H "003EB"H "004EB"H "005EB"H "006EB"H "007EB"H "008EB"H "009EB"H "00AEB"H "00BEB"H "00CEB"H "00DEB"H "00EEB"H "00FEB"H "010EB"H "011EB"H "012EB"H "013EB"H
......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... ......... .........
"00001"H "00101"H "00201"H "00301"H "00401"H "00501"H "00601"H "00701"H "00801"H "00901"H "00A01"H "00B01"H "00C01"H "00D01"H "00E01"H "00F01"G "01001"H "01101"H "01201"H "01301"H
"00000"H "00100"H "00200"H "00300"H "00400"H "00500"H "00600"H "00700"H "00800"H "00900"H "00A00"H "00B00"H "00C00"H "00D00"H "00E00"H "00F00"H "01000"H "01100"H "01200"H "01300"H
......
......
......
......
......
......
......
Line 319 Line 320
"13EFF"H "13FFF"H
"13EFE"H "13FFE"H
"13EFD"H "13FFD"H
"13EFC"H "13FFC"H
"13EEB"H "13FEB"H
"13E01"H "13F01"H
"13E00"H "13F00"H
Rev.1.11, Oct. 02.2003, page 27 of 175
......
HD66776 Relation between GRAM data and Display contents (SS = "1")
80-system 18-bit interface
GRAM Data DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB DB 8 7 DB 6 DB 5 DB DB 4 3 DB 2 DB 1 DB 0
RGB Arrangement R5 Output Pins Output BGR = "0" order BGR = "1"
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Sn + 1 1 3 2 2 3 1 Note: n = lower eight bit of address (255 to 0)
80-system 16-bit interface
GRAM Data DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB DB 8 7 DB 6 DB 5 DB DB 4 3 DB 2 DB 1
RGB Arrangement R5 Output Pins Output BGR = "0" order BGR = "1"
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Sn + 1 1 3 2 2 3 1 Note: n = lower eight bit of address (255 to 0)
80-system 9-bit interface
First transfer
GRAM Data DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB DB 9 17 DB 16
Second transfer
DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB 9
RGB Arrangement R5 Output Pins Output BGR = "0" order BGR = "1"
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Sn + 1 1 3 2 2 3 1 Note: n = lower eight bit of address (255 to 0)
80-system 8-bit interface (1)
First transfer GRAM Data DB 17 DB 16 DB DB 15 14 DB 13
(Two timas transfer/pixel)
Second transfer DB 12 DB 11 DB 10 DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10
RGB Arrangement R5 Output Pins Output BGR = "0" order BGR = "1"
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Sn + 1 1 3 2 2 3 1 Note: n = lower eight bit of address (255 to 0)
Rev.1.11, Oct. 02.2003, page 28 of 175
HD66776
80-system 8-bit interface (2) (Three timas transfer/pixel)
Sec nd tran sf r o e DB DB 11 10 DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10 Thi t ransf r rd e DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10
Fi tran sf r rst e
GRAM D ata
RGB Arra ng em ent Ou tput P ins Ou tput BG R = "0" orde r BG R = "1"
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Sn + 1 1 3 2 2 3 1 Note: n = lower eight bit of address (255 to 0)
80-system 8-bit interface (3)
First transfer GRAM D ata
(Three timas transfer/pixel)
Second transfer DB DB DB DB DB DB 17 16 15 14 13 12 Thrid transfer DB DB DB DB DB DB 17 16 15 14 13 12
DB DB DB DB DB DB 17 16 15 14 13 12
RGB Arra ng em ent Ou tput P ins Ou tput orde r BG R = "1" BG R = "0"
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Sn + 1 1 3 2 2 3 1 Note: n = lower eight bit of address (255 to 0)
SPI (Two times transfer/pixel)
First transfer GRAM D ata DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 Second transfer DB 14 DB 13 DB 12 DB 11 DB 10
RGB Arra ng em ent Ou tput P ins Ou tput BG R = "0" orde r BG R = "1"
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Sn + 1 1 3 2 2 3 1
Note: n = lower eight bit of address (255 to 0)
Rev.1.11, Oct. 02.2003, page 29 of 175
HD66776
18-bit RGB interface
GRA M Dat a PD 17 PD 16 PD 15 PD 14 PD 13 PD 12 PD 11 PD 10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1 PD 0
RGB Arra ng em ent Ou tput P ins Ou tput BG R = "0" orde r BG R = "1"
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Sn + 1
Note: n = lower eight bit of address (255 to 0)
16-bit RGB interface
GRAM D ata PD 17 PD 16 PD 15 PD 14 PD 13 PD 11 PD 10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 PD 2 PD 1
RGB Arra ng em ent Ou tput P ins Ou tput BG R = "0" orde r BG R = "1"
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Sn + 1
Note: n = lower eight bit of address (255 to 0)
6-bit RGB interface
First transfer GRAM D ata PD 17 PD 16 PD 15 PD 14 PD 13 PD 12 PD 17 Second transfer PD 16 PD 15 PD 14 PD 13 PD 12 PD 17 Third ransfer PD 16 PD 15 PD 14 PD 13 PD 12
RGB Arra ng em ent Ou tput P ins Ou tput BG R = "0" orde r BG R = "1"
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Sn + 1
Note: n = lower eight bit of address (255 to 0)
Rev.1.11, Oct. 02.2003, page 30 of 175
HD66776
Instructions
Outline The HD66776 has an 18-bit bus architecture. Before the internal operation of the HD67766 starts, control information is temoralily sotred in the registers descreibed below to allow high-speed interfaceing with a high-performance microcomputer. The internla operation of the HD66776 is determined by signals sent from the microcomputer. These signals, which include the register selection signal (RS), the read/write signal (R/"), and the internal 16-bit data bus signals (DB15 to DB0), make up the HD6776 instructions. The accesses to the GRAM use the internal 180bit data bus. There are nine categories of instructions. Specify the index Read the status Control the display Control power management Process the graphics data Set internal GRAM addresses Transfer data to and from the internal GRAM Set grayscale level for the internal grayscale -adjustment Interface with the gate driver and power supply IC
Normally, instructions that write data are used the most. However, an auto-update of internal GRAM addresses after each data write can reduce the amount of transferred data and lighten the microcomputer program load with the window address function. The 16-bit instruction assignments (IB15-0) differ according to the interface as is shown below. Issuing of instructions should be in accord with the data format in use.
80-system 18-bit interface
DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB DB 8 7 DB 6 DB 5 DB DB 4 3 DB 2 DB 1 DB 0
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB IB 54
IB 3
IB 2
IB 1
IB 0
Rev.1.11, Oct. 02.2003, page 31 of 175
HD66776
80-system 16-bit nterface
DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB DB 8 7 DB 6 DB 5 DB DB 4 3 DB 2 DB 1
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
80-system 9-bit nterface
First transfer DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB DB 9 17 DB 16 Second transfer DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB 9
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
80-system 8-bit nterface
First transfer DB 17 DB 16 DB DB 15 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 Second transfer DB DB 15 14 DB 13 DB 12 DB 11 DB 10
Instruction Bit (IB)
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Rev.1.11, Oct. 02.2003, page 32 of 175
HD66776 Instruction Description Ensure that you are aware of the assignments of instruction bits (IB15-0) for each interface that are illustrated below. General Settings Index The index instruction specifies the RAM control indexes (R000h to R40Fh). It sets the register number in the range of "00000000000" to "10000001111" in binary form. Those instruction bits of the index register which are not allocated to the index register should not be accessed.
R/W W RS 0 IB15 IB14 IB13 IB12 IB11 IB10 ID10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
*
*
*
*
*
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Start Oscillation (R000h) The start oscillation instruction restarts the oscillator from the halt state in the standby mode. After issuing this instruction, wait at least 10 ms for oscillation to stabilize before issuing the next instruction. (See the Standby Mode section.) If this register is read forcibly, 0776H is read.
R/W W R RS 1 1 IB15 IB14 IB13 IB12 IB11 IB10 * 1 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
*
0
*
0
*
0
*
0
*
0
*
1
*
1
*
0
*
1
*
1
*
1
*
0
*
1
*
1
1
0
Driver Output Conrol (R001h)
R/W W RS 1 IB15 0 IB14 0 IB13 0 IB12 0 IB11 0 IB10 0 IB9 0 IB8 SS IB7 0 IB6 0 IB5 NL5 IB4 NL4 IB3 NL3 IB2 NL2 IB1 NL1 IB0 NL0
SS: Selects the output shift direction of the source driver. When SS = 0, the sequence is from S1 to S256. When SS = 1, the sequence is from S256 to S1. In addition, SS and BGR bits should be specified when the bit order for R, G, and B are changed. When BGR = 0, the output order is R, G, and B. When BGR = 1, the output order is R, G, and B. Rewrite data to the RAM whenever you change the SS and BGR bits.
NL5-0: Specify the number of raster-rows to be driven. The number is adjusted in units of eight. Mapping of addresses in the GRAM is independent of this setting. The selected size should be larger than the panel to be driven.
Rev.1.11, Oct. 02.2003, page 33 of 175
HD66776 NL Bits
NL5 0 0 0 0 0 0 0 0 0 NL4 0 0 0 0 0 0 0 0 0 NL3 0 0 0 0 0 0 0 0 1 NL2 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 NL1 0 0 1 1 0 0 1 1 0 NL0 0 1 0 1 0 1 0 1 0 Display Size Setting disabled 256 x 16 dots 256 x 24 dots 256 x 32 dots 256 x 40 dots 256 x 48 dots 256 x 56 dots 256 x 64 dots 256 x 72 dots 256 x 280 dots 256 x 288 dots 256 x 296 dots 256 x 304 dots 256 x 312 dots 256 x 320 dots LCD Raster-Rows Setting disabled 16 24 32 40 48 56 64 72 280 288 296 304 312 320
Note: A front porch period (set in the FP register) and back porch period (set in the BP register) will respectively be inserted as blank periods (all gates output Vgoff level) before and after the driver scans through all of the gates.
LCD-Driving-Waveform Control (R002h)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
0
0
0
0
0
0
B/C
EOR
0
0
NW 5
NW 4
NW 3
NW 2
NW 1
NW 0
B/C: When B/C = "0", a frame-AC waveform is generated and the LCD-driving signal alternates frame by frame. When B/C = "1", an n-raster-row AC waveform is generated and its polarity alternates on each raster-row specified by bits EOR and NW5-NW0 of the LCD-driving-waveform control register. For details, see the section on the n-raster-row reversed AC drive. EOR: When the C-pattern waveform is set (B/C = "1") and EOR = "1", the odd/even frame-select signals and the n-raster-row reversed signals are EORed for alternating drive. EOR is used when the LCD is not alternated the set values of the LCD drive duty ratio and the n raster-row. For details, see the n-raster-row Reversed AC Drive section.
Rev.1.11, Oct. 02.2003, page 34 of 175
HD66776 NW5-0: Specify the number of raster-rows n that will alternate at the C-pattern waveform setting (B/C = "1"). NW5-NW0 alternate for every set value + 1 raster-row, and the first to the 64th raster-rows can be selected. Entry Mode (R003h)
R/W W RS 1 IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
TRI
DEM
0
BGR
0
0
HWM 1
HWM 0
0
0
I/D 1
I/D 0
AM
0
0
0
The write data sent from the microcomputer is modified in the HD66776 and written to the GRAM. The display data in the GRAM can be quickly rewritten to reduce the load of the microcomputer software processing. For details, see the Graphics Operation Function section. HWM1-0: When HWM=11, data can be written to the GRAM at high speed. In high-speed write mode, four words of data are written to the GRAM in a single operation after writing to RAM four times. Write to RAM four times, otherwise the four words cannot be written to the GRAM. Thus, set the lower 2 bits to 0 when setting the RAM address. For details, see High-Speed RAM Write Mode section. I/D1-0: When I/D1-0 = "1", the address counter (AC) is automatically incremented by 1 after the data is written to the GRAM. When I/D1-0 = 0, the AC is automatically decremented by 1 after the data is written to the GRAM. The increment/decrement setting of the address counter by I/D1-0 is done independently for the upper (AD16-8) and lower (AD7-0) addresses. The direction of moving through the addresses when the GRAM is written to is set by the AM bit. AM: Sets the automatic update method of the AC after the data is written to the GRAM. When AM = "0", the data is continuously written horizontally. When AM = "1", the data is continuously written vertically. When window address range is specified, the GRAM in the window address range can be written to according to the I/D1-0 and AM settings.
Rev.1.11, Oct. 02.2003, page 35 of 175
HD66776
Direction Setting
I/D1-0 = "00" Horizontal: Decrement Vertical: Decrement
00000h
I/D1-0 = "01" Horizontal: Increment Vertical: Decrement
00000h
I/D1-0 = "10" Horizontal: Decrement Vertical: Increment
00000h
I/D1-0 = "11" Horizontal: Increment Vertical: Increment
00000h
AM = "0" Horizontal
13FFFFh 0000h 0000h
13FFFFh 0000h
13FFFFh 0000h
13FFFFh
AM = "1" Vertical
13FFFFh
13FFFFh
13FFFFh
13FFFFh
Address direction setting
BGR: In the writing of 18 bits of data to RAM, this bit may be used to reverse the bit order from R, G, and B to B, G, and R. Please be aware that setting BGR to 1 will convert the order of the CP17-0 and WM17-0 bits in the same way.
Rev.1.11, Oct. 02.2003, page 36 of 175
HD66776
BGR = "0"
18-bits
Write data to GRAM*1
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Conversion of RGB to BGR and vice versa
Write data to GRAM (WM17-0)*2
Write data mask (WM17-0)
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2 B1
B0
GRAM
BGR = "1"
18-bits
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Conversion of RGB to BGR and vice versa
Write data mask (WM17-0)
B5
B4
B3
B2
B1
B0
G5
G4
G3 G2
G1
G0
R5
R4
R3
R2
R1
R0
GRAM
Note1: Data is written to the GRAM in 18-bit units. Logical and compare operations are also performed in 18-bit units. For bit assignment for each interface, see the section parallel transfer. Note2: The write data mask (WM17-0) is set by the register in the RAM write data mask section.
TRI: Set transforming method for 80 system 8-bit bus interface. DFM: Set data format of TRI = "1" for 80 system 8-bit bus interface.
Rev.1.11, Oct. 02.2003, page 37 of 175
HD66776
TRI = "1", DFM = "0" First transfer GRAM Data
DB DB 11 10
Second transfer
DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10
Third transfer
DB DB DB DB DB DB DB DB 17 16 15 14 13 12 11 10
RGB Arrangement
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
TRI = "1", DFM = "1" First transfer GRAM Data
DB DB DB DB DB DB 17 16 15 14 13 12
Second transfer
DB DB DB DB DB DB 17 16 15 14 13 12
Third transfer
DB DB DB DB DB DB 17 16 15 14 13 12
RGB Arrangement
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
DFM Setting TRI = 0 RAM write (65k color mode) 65k color display
Pin setting (8-bit two times transfer/three times transfer) IM3 =GND IM2 =GND IM1 =Vcc IM0 = Vcc
TRI = 1 RAM write (262k color mode) 262k color display
Note 1.Setting Index and Common are two-times transfer no matter if it is set as three-times transfer mode. 2.It does not read data when it is set as three-times transfer mode.
8-bit two-times transfer/three-times transfer setting flow
Rev.1.11, Oct. 02.2003, page 38 of 175
HD66776 Display Control (1) (R007h)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
COL
0
0
0
0
VLE 2
VLR 1
SPT
PT1
PT0 GON DTE
0
REV
D1
D0
VLE2-1: When VLE = "1", the first screen is vertically scrolled. When VLE2 = "1", the 2nd screen is vertically scrolled. Note: This function is not available when the external display interface is in use. When using an external display interface, VLE2-1must be set to "00". VLE Bits
VLE2 0 0 1 1 VLE1 0 1 0 1 Image on 1 Screen Stationary Stationary Scroll Scroll
st
Image on 2 Stationary Scrolled Stationary Scroll
nd
Screen
COL: When COL = "1", selects the eight color display mode. For details, see the section on the eight-color dipslay mode. CL Bits
COL o 1 Number of Colors 262,144 8
SPT: SPT = "1" selects the two-division driving of the LCD. For details, see the section on the screendivision driving function. Note: This function is not available when the external display interface is in use. When using an external display interface, SPT must be set to "0". REV: REV = 1 selects the inversion of the display of all characters and graphics. For details, see the section on the inverted display function. Making it possible to invert the grayscale levels allows the display of the same data on both normally white and normally black panels. The output on the source lines during the periods of the front and back porch and blanking of the partial display is determined by PT1-0.
Rev.1.11, Oct. 02.2003, page 39 of 175
HD66776
REV GRAM Data 18'h00000 0 18'h3FFFF 18'h00000 1 18'h3FFFF V63 V0 V0 V0 V63 V63 Note: The output on the source lines during the periods of the front and back porch and blanking of the partial display is determined by PT1-0. Source Output in the Display Area* Positive Polarity Negative Polarity V63 V0
PT1-0: Normalize the source outputs when non-displayed area of the partial display is driven. For details, see the section on screen-division driving function. PT Bits
PT1 0 0 1 1 PT0 0 1 0 1 Source Output for Non-Display Area Positive Polarity V63 V63 GND High impedance Negative Polarity V0 V0 GND High impedance Normal Drive "Low" "Low" "Low" DISPTMG Output for Non-Display Area
GON: When GON = "0", the gate-off level and Vcom level will be GND. DTE: When DTE = "0", the DISPTMG output will be fixed to GND. DTE Bits
DTE 0 1 DISPTMG Output Halt (GND) Operation (Vcc/GND)
D1-0: The display is on when D1 = 1 and off when D1 = 0. When the display is off, the data for display is retained in the GRAM, and can instantly be redisplayed by setting D1 = 1. When D1 is 0 (i.e., the display is off) all of the source outputs are set to the GND level. This allows the HD66776 to control the charging current for the LCD during AC driving. When D1-0 = 01, the internal display operations of the HD66776 continue although the actual display is off. When D1-0 = 00, the internal display operations halt and the display is also switched off. These bits, in combination with GON and DTE, control the display. For details, see the section on the flow for setting instructions.
Rev.1.11, Oct. 02.2003, page 40 of 175
HD66776 D1-0 Bits
HD67776 Internal Operations Halt Operate Operate Operate Power supply IC and LCD panel Control Signals (FLM, SFTCLK1/2, CLA/B/C, DCCLK, EQ) Halt Operate Operate Operate
D1
D0
Source Output
0 0 1 1
0 1 0 1
GND GND Unlit display Display
Note: Data can be written to the GRAM from the microcomputer regardless of the contents of D1-0. Note: The GON bit is used to set the power supply IC. Control by the power supply is according to this bit's value. For details, see the data sheet for the power supply IC.
Rev.1.11, Oct. 02.2003, page 41 of 175
HD66776 Display Control 2 (R008h)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
0
0
0
0
FP3 FP2
FP1
FP0
0
0
0
0
BP3 BP2
BP1 BP0
FP3-0/BP3-0: Set the periods of blanking (the front and back porch), which are placed at the beginning and end of the display. FP3-0 are for a front porch and BP3-0 are for a back porch. When the external display interface is in use, the front porch (FP) will start on the falling edge of the VSYNC signal and display operation commences at the end of the front-porch period. The back porch (BP) will start when data for the number of raster-rows specified by the NL bits has been displayed. During the period between the completion of the back-porch period and the next VSYNC signal, the display will remain blank. FP and BP Bits
FP3 BP3 0 0 0 0 0 FP2 BP2 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 FP1 BP1 0 0 1 1 0 FP0 BP0 0 1 0 1 0 Number of Raster Periods in the Front Porch Number of Raster Periods in the Back Porch Setting disabled Setting disabled 2 3 4 12 13 14 Setting disabled
VSYNC Back porch Display area
Front porch
Note: The output timing to LCD panels displayed two raster-rows after the input synchronization signal.
Instruction for setting BP/FP Set BP and FP within the range indicated below.
Internal clock operation RGB interface VSYNC interface BP >= 2 lines BP >= 2 lines BP >= 2 lines FP >= 2 lines FP >= 2 lines FP >= 2 lines FP + BP <= 16 lines FP + BP <= 16 lines FP + BP = 16 lines
Rev.1.11, Oct. 02.2003, page 42 of 175
HD66776 Gate Driver Interface Control (R00Ah)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W R
1 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
TE TE
0 0
0 0
0 0
0 0
0 0
IDX2 IDX2
IDX1 IDX0 IDX1 IDX0
IDX2-0: Index bits that select instructions for the gate-driver/power-supply IC. The instruction that corresponds to the setting made here is transferred, with the index, to the gate-driver/power-supply IC via the serial interface. These instructions are transferred in bit rows as shown below. The upper 3 bits correspond to IDX2-0. The IDX2-0 setting at the time of transfer selects the instruction for the gatedriver/power-supply IC as listed below. To change an instruction setting on the gate-driver/power-supply IC, first change the instruction bit on the HD66776, select the instruction, which includes the changed instruction bit, from the list below, by setting IDX2-0 as required. The instruction is transferred to the gate-driver/power-supply IC as the transfer starts (TE=1), and is the executed. TE: Serial transfer enable for the gate-driver/power-supply IC. When TE=0, serial transfer is possible. Do not change the instruction during transfer. When TE=1, transfer starts. TE returning to 0 indicates the end of the transfer. Note that, serial transfer to the gate-driver/power-supply IC requires 18 clock cycles at most. Do not change the instruction during the transfer. * New instructions should be transferred to the gate-driver/power-supply IC soon after they have been set on the HD66776. HD667P20 Instruction chart
IDX2 0 IDX1 0 IDX0 0 DB12 DB11 DB10 DB9 0 0 0 0 1 0 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 0 0 GON
(VRL3) 0 (VRL3) 1
DB8 BT1
VRL0
DB7 BT0
PON
DB6 DC2
VRH3
DB5 DC1
VRH2
DB4 DC0
VRH1
DB3 AP2
VRH0
DB2 AP1
VC2
DB1 AP0
VC1
DB0 SLP
VC0
VCO MG
VRL2
BT2
VRL1
0 0
0
DK0
0
0
0
0
0
0
0
0
0
VDV4 VDV3 VDV2 VDV1 VDV0 VCM4 VCM3 VCM2 VCM1 VCM0 Setting inhibited Setting inhibited Setting inhibited Setting inhibited
VGL4 VGL3 VGL2 VGL1 VGL0
0
VGH4 VGH3 VGH2 VGH1 VGH0
Rev.1.11, Oct. 02.2003, page 43 of 175
HD66776
Instruction setting change
Change the instruction bit setting corresponding to the HD66776.
Transfer to the power-supply IC must be executed immediately after setting up the instruction. Index set R00Ah Instruction read NO (During transfer) TE = "0" YES (Transfer can be executed) Power-supply side index (IDX2 to 0) TE = 1 (transfer start) Specify the IDX2 to 0 bits to according to the list of the instructions for a power supply. These bits should correspond to the setting to which they were charged in the first operation of this flow chart.
Power supply IC interface: Serial transfer sequence
Notes 1: Transfer to the power-supply IC must take place immediately after setting up the instruction. 2: The serial transfer period takes a maxim of 1/fosc x 18clock cycles (sec). 3: Serial transfer cannot be executed in standby mode. If the chip enters standby mode during transfer, the serial transfer is forcibly suspended. Transfer must be executed again because correct transfer, tis not guaranteed in this situation. 4: Serial transfer can be forcibly suspended by writing TE = 0. Transfer must be executed again because correct transfer is not guaranteed in this situation. 5. Do not enter standby mode during transfer forcibly terminate transfer except incase of emergency. Before executing, confirm that the transfer is completed.
Rev.1.11, Oct. 02.2003, page 44 of 175
HD66776 External Display Interface Control 1) (R00Ch)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
0
0
0
0
0
0
0
RM
0
0
DM1 DM0
0
0
RIM1 RIM0
RIM1-0: Specify the RGB I/F mode when the RGB interface is used. Specifically, this setting specifies the mode when the bits of DM and RM are set to RGBI/F. These bits should be set before display operation through the RGB I/F and should not be set during operation. RIM Bits
RIM1 0 0 1 1 RIM0 0 1 0 1 RGB Interface Mode 18-bit RGB interface (one-time transfer/pixel) 16-bit RGB interface (one-time transfer/pixel) 6-bit RGB interface (three-time transfers/pixel) Setting disabled
DM1-0:.Specify the display operation mode. The interface can be set based on the bits of DM1-0. This setting enables switching interfaces between internal operation and the external display interface. Switching between two external display interfaces (RGB-I/F and VSYNC-I/F) should not be done. DM Bits
DM1 0 0 1 1 DM0 0 1 0 1 Display Interface Internal clock operation RGB interface VSYNC interface Setting disabled
RM: Specifies the interface for RAM accesses. RAM accesses can be performed through the interface specified by the bits of RM1-0. When the display data is written via the RGB-I/F, 1 should be set. This bit and the DM bits can be set independently. The display data can be rewritten via the system interface by clearing this bit while the RGB interface is used. RM Bits
RM 0 1 Interface for RAM Access System interface/VSYNC interface RGB interface
Rev.1.11, Oct. 02.2003, page 45 of 175
HD66776 Depending on the external display interface settings, different interfaces for use can be specified to match the displaying state. While displaying moving pictures (RGB-I/F/VSYNC-I/F), the data for display can be written in high-speed write mode (HWM = "11"), which achieves both low power consumption and highspeed access. Display state and interfaces
Display State Still pictures Moving pictures Rewrite still picture area while displaying moving pictures. Moving pictures Note Operation Mode Internal clock operation RGB interface (1) RAM Access (RM) System interface (RM = 0) RGB interface (RM = 1) System interface (RM = 0) System interface (RM = 0) Display Operation Mode (DM1-0) Internal clock operation (DM1-0 = 00) RGB interface (DM1-0 = 01) RGB interface (DM1-0 = 01) VSYNC interface (DM1-0 = 10)
RGB interface (2)
VSYNC interface
1 :The instruction register can only be set through the system interface. 2 :Switching between RGB-I/F and VSYNC-I/F cannot be done. 3 :The RGB-I/F mode should not be changed during RGB I/F operation. 4 :For the transition flow for each operation mode, see the External Display Interface section. 5 :RGB-I/F and VSYNC-I/F should be used in high-speed write mode (HWM1-0 = "11").
Internal clock operation mode All the display operations are controlled by signals generated by the internal clock in internal clock operation mode. All inputs through the external display interface are invalid. The internal RAM can be accessed only via the system interface. RGB interface mode (1) The display operations are controlled by the frame synchronization clock (VSYNC), raster-row synchronization signal (VSYNC), and dot clock (DCLK) in RGB interface mode. These signals should be supplied during display operation in this mode. The display data is transferred to the internal RAM via PD17-0 for each pixel. Combining the function of the high-speed write mode and the window address enables display of both the moving picture area and the internal RAM area simultaneously. In this method, data is only transferred when the screen is updated, which reduces the amount of data transferred. The periods of the front (FP) and back (BP) porch and the display are automatically generated in the HD66776 by counting the raster-row synchronization signal (HSYNC) based on the frame synchronization signal (VSYNC). When pixel data is transferred via PD 17 to 0, the transfer should be operated according to the settings above. RGB interface mode (2) When RGB-I/F is in use, data can be written to RAM via the system interface. This write operation should be performed while data for display is not being transferred via RGB-I/F (ENABLE = High). Before the next data transfer for display via RGB-I/F, the setting above should be changed, and then the address and index (R202h) should be set.
Rev.1.11, Oct. 02.2003, page 46 of 175
HD66776 VSYNC interface mode The internal display operation is synchronized with the frame synchronization signal (VSYNC) in VSYNC interface mode. When data is written to the internal RAM with the required speed after the falling edge of VSYNC, moving pictures can be displayed via the conventional interface. There are some limitations on the timing and methods of writing to RAM. See the section on the external display interface. In VSYNCI/F mode, only the VSYNC input is valid. The other input signals for the external display interface are invalid. The periods of the front porch (FP), back porch (BP), and display period (NL) are automatically generated by the frame synchronization signal (VSYNC) according to the settings of the HD66776 registers.
Rev.1.11, Oct. 02.2003, page 47 of 175
HD66776 Frame Cycle Control (1) (R00Dh)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
0
0
0
0
0
0
DIVI 1
DIVI 0
0
0
0
RTNI RTNI RTNI 4 3 2
RTNI RTNI 1 0
RTNI4-0: Set the 1H period (1 raster-row). DIVI1-0: Set the division ratio of clocks for internal operation (DIVI1-0). Internal operations are driven by clocks, which are frequency divided according to the DIVI1-0 setting. Frame frequency can be adjusted along with the 1H period (RTNI4-0). When changing the number of raster-rows, adjust the frame frequency. For details, see the frame frequency adjustment Function section. RTNI Bits and Clock Cycles
RTNI4 0 RTNI3 0 RTNI2 0 RTNI1 0 RTNI0 0 Setting disabled 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 1 0 Clock number for one line
16 clock 17 clock 18 clock
1 1
1 1
1 1
1 1
0 1
30 clock 31 clock
DIVI Bits and Clock Frequency
DIVI1 0 0 1 1 DIVI0 0 1 0 1 Division Ratio 1 2 4 8 Internal Operating Clock Frequency fosc / 1 fosc / 2 fosc / 4 fosc / 8
* fosc = R-C oscillation frequency Formula for the frame frequency
Frame frequency = fosc Clock cycles per raster-row x division ratio x (Line + FP + BP) [Hz]
fosc: R-C oscillation frequency Line: number of driven raster-rows (NL bit) FP: Front porch BP: Back porch Division ratio: DIVI bit Clock cycles per raster-row: RTNI bit
Rev.1.11, Oct. 02.2003, page 48 of 175
HD66776 External Display Interface Control (2) (R00Eh)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
0
0
0
0
0
0
DIVE 1
DIVE RTNE RTNE RTNE RTNE RTNE RTNE RTNE RTNE 0 7 6 5 4 3 2 1 0
RTNE7-0: Sets the 1H period (1-raster-row). Sets DOTCLK for 1H divided by division ratio.
RTNE7 0 RTNE6 0 RTNE5 0 RTNE4 0 : : 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 : : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0 1 0 0 0 1 0 0 1 1 0 1 0 16 clock 17 clock 18 clock : : 254 clock 255 clock RTNE3 0 RTNE2 0 RTNE1 0 RTNE0 0 Setting inhibited Number of Clock for 1 period
DIVE1-0: Set the internal division ratio of DOTCLK clocks (DIVE1-0). Internal operations are driven by clocks which frequency are divided according ot the DIVE1-0.
DIVE1 0 0 1 1
DIVE0 0 1 0 1
Division Ratio 2 4 8 16
Frequency of internal DOTCLK 18/16 bit RGB interface Setting inhibited fdotclk / 4 fdotclk /8 fdotclk /16 6 bit RGB interface Setting inhibited fdotclk / 12 fdotclk /24 fdotclk /48 * fdotclk : R-C oscillation frequency
Rev.1.11, Oct. 02.2003, page 49 of 175
HD66776 External Display Interface Control (3) (R00Fh)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
0
0
0
0
0
0
0
0
0
0
0
VSPL HSPL VPL
EPL
DPL
DPL: Sets the signal polarity of DOTCLK pin. DPL = "0": Read data at rising edge of DOTCLK. DPL = "1": Read data at falling edge of DOTCLK. EPL: Sets the signal polarit of ENABLE pins. EPL = "0": When ENABLE ="low", it is available to write data of PD17-0. When ENABLE = "high", it is not available to write data of PD17-0. EPL = "1": When ENABLE = "high", it is available to write data of PD17-0. When ENBALE = "low", it is not available to write data of PD17-0. VPL: Sets te signal polarity of VLD pin. VPL = "0": When VLD = "Low", RAM writing is available. When VLD = "High", RAM writing is not available. VPL = "1": When VLD = "high", RAM writing is available. When VLD ="low", RAM writing is not available.
HSPL: Sets the signal polarity of HSYNC pin. HSPL = "0": "Low" is active. HSPL = "1": "High" is active VSPL: Set the signal polarity of VSYNC pin. VSPL = "0": "Low" is active. VSPL = "1": "High" is active.
Rev.1.11, Oct. 02.2003, page 50 of 175
HD66776 LTPS Interface Control (1) (R010h)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
0
0
FWI 5
FWI 4
FWI FWI 2 3
FWI 1
FWI 0
0
0
0
0
0
FTI 2
FTI 1
FTI 0
FTI2-0: Defines the FLM rising position. FWI5-0: Sets the "High" width of FLM.
FTI2 0 0 0 0 1 1 1 1 FTI1 0 0 1 1 0 0 1 1 FTI0 0 1 0 1 0 1 0 1 FLM rising position 0 clock 0.5 clock 1 clock 1.5 clock 2.0 clock 2.5 clock 3 clock 3.5 clcok
Note) Numbers in the above chart show the rising position of FLM signal from 0 clock when setting SFTCLK rising point on 0 clock.
FWI5 0 0 0 0 0 0 0 0 : : 1
FWI4 0 0 0 0 0 0 0 0 : : 1
FWI3 0 0 0 0 0 0 0 0 : : 1
FWI2 0 0 0 0 1 1 1 1 : : 1
FWI1 0 0 1 1 0 0 1 1 : : 1
FWI0 0 1 0 1 0 1 0 1 : : 1
FLM "High" period 0 clock 0.5 clock 1 clock 1.5 clock 2 clock 2.5 clock 3 clock 3.5 clock : : 31.5 clock
Rev.1.11, Oct. 02.2003, page 51 of 175
HD66776 LTPS Interface Control (2) (R011h)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
0
0
SWI 5
SWI 4
SWI SWI 3 2
SWI 1
SWI 0
0
0
0
0
0
STI 2
STI 1
STI 0
STGI2-0: Defines the SFTCLK1 and 2 rising position. SWI5-0: Sets the "High" width of SFTCLK1 and 2.
STI2 0 0 0 0 1 1 1 1 STI1 0 0 1 1 0 0 1 1 STI0 0 1 0 1 0 1 0 1 SFTCLK rising position 0 clock 0.5 clock 1.0 clock 1.5 clock 2.0 clock 2.5 clock 3 clock 3.5 clcok
Note) Numbers in the above chart show the rising position of FLM signal from 0 clock when setting SFTCLK rising point on 0 clock.
SWI5 0 0 0 0 0 0 0 0 : : 1
SWI4 0 0 0 0 0 0 0 0 : : 1
SWI3 0 0 0 0 0 0 0 0 : : 1
SWI2 0 0 0 0 1 1 1 1 : : 1
SWI1 0 0 1 1 0 0 1 1 : : 1
SWI0 0 1 0 1 0 1 0 1 : : 1
SFTCLK "High" period 0 clock 0.5 clock 1 clock 1.5 clock 2 clock 2.5 clock 3 clock 3.5 clock : : 31.5 clock
Rev.1.11, Oct. 02.2003, page 52 of 175
HD66776 LTPS Interface Control (3) (R012h)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
0
0
0
CLWI CLWI CLWI CLWI 4 3 2 1
CLWI 0
0
0
0
0
CLTI 3
CLTI 2
CLTI 1
CLTI 0
CLTI3-0: Defines the CLA rising position. CLW
CLTI3 0 0 0 0 0 CLTI2 0 0 0 0 1 CLTI1 0 0 1 1 0 CLTI1 0 1 0 1 0 CLA rising position Setting disabled 0.5 clock 1.0 clock 1.5 clock 2.0 clock
1
1
1
1
7.5 clcok
Note) Numbers in the above chart show the rising position of FLM signal from 0 clock when setting SFTCLK rising point on 0 clock.
CLWI4 0 0 0 0 0 0 0 0 : : 1
CLWI3 0 0 0 0 0 0 0 0 : : 1
CLWI2 0 0 0 0 1 1 1 1 : : 1
CLWI1 0 0 1 1 0 0 1 1 : : 1
CLWI0 0 1 0 1 0 1 0 1 : : 1
CLA/B/C "High" period 0 clock 0.5 clock 1 clock 1.5 clock 2 clock 2.5 clock 3 clock 3.5 clock : : 15.5 clock
Rev.1.11, Oct. 02.2003, page 53 of 175
HD66776 LTPS Interface Control (4) (R013h)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
0
0
0
CLWI CLWI CLWI CLWI 4 3 2 1
CLWI 0
0
0
0
0
CLTI 3
CLTI 2
CLTI 1
CLTI 0
DPTI2-0: Defines the DISPTMG rising position. DPWI5-0: Sets the "High" width of DISPTMG.
DPTI2 0 0 0 0 1 : 1 DPTI1 0 0 1 1 0 : 1 DPTI0 0 1 0 1 0 : 1 DISPTMG rising position 0 clock 0.5 clock 1.0 clock 1.5 clock 2.0 clock : 3.5 clcok
Note) Numbers in the above chart show the rising position of FLM signal from 0 clock when setting SFTCLK rising point on 0 clock.
DPWI5 0 0 0 0 0 0 0 0 : : 1
DPWI4 0 0 0 0 0 0 0 0 : : 1
DPWI3 0 0 0 0 0 0 0 0 : : 1
DPWI2 0 0 0 0 1 1 1 1 : : 1
DPWI1 0 0 1 1 0 0 1 1 : : 1
DPWI0 0 1 0 1 0 1 0 1 : : 1
CLA/B/C "High" period 0 clock 0.5 clock 1 clock 1.5 clock 2 clock 2.5 clock 3 clock 3.5 clock : : 31.5 clock
Rev.1.11, Oct. 02.2003, page 54 of 175
HD66776 LTPS Interface Control (5) (R014h)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
0
0
0
0
0
MCPI MCPI 2 1
MCPI 0
0
0
0
0
0
0
SHI 1
SHI 0
SHI1-0: Defines the hold time from the falling edge of CLA/B/C source output. MCPI2-0: Sets the changing position of AC signal M.
SHI1 0 0 1 1 SHI0 0 1 0 1 Source hold time 0 clock 0.5 clock 1.0 clock 1.5 clock
Note) Setting values above are clocks from the falling edge of CLA, CLB, and CLC signals.
MCPI2 0 0 0 0 1 1 1 1
MCPI1 0 0 1 1 0 0 1 1
MCPI0 0 1 0 1 0 1 0 1
M alternating point 0 clock 0.5 clock 1 clock 1.5 clock 2 clock 2.5 clock 3 clock 3.5 clock
Note) Numbers in the above chart show the rising position of FLM signal from 0 clock when setting SFTCLK rising point on 0 clock.
Rev.1.11, Oct. 02.2003, page 55 of 175
HD66776 LTPS Interface Control (6) (R015h)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
0
0
0
0
0
0
EQWI EQWI 1 0
0
0
0
0
0
EQTI EQTI EQTI 2 1 0
ETQI2-0: Defines the equalize starting position. EQWI1-0: Sets "High" width of EQ.
EQTI2 0 0 0 0 1 1 1 1 EQTI1 0 0 1 1 0 0 1 1 EQTI0 0 1 0 1 0 1 0 1 Equalize starting position 0 clock 0.5 clock 1.0 clock 1.5 clock 2 clock 2.5 clock 3 clock 3.5 clock
Note) Numbers in the above chart show the rising position of FLM signal from 0 clock when setting SFTCLK rising point on 0 clock.
EQWI1 0 0 1 1
EQWI0 0 1 0 1
EQ "High" period 0 clock 0.5 clock 1 clock 1.5 clock
Rev.1.11, Oct. 02.2003, page 56 of 175
HD66776 LTPS Interface Control (7) (R016h)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
FEW FEW 7 6
FEW FEW FEW FEW 5 4 3 2
FEW 1
FEW 0
0
0
0
FTE 4
FTE 3
FTE 2
FTE 1
FTE 0
FTE4-0: Defines the FLM rising position. FWE7-0: Sets the "High" width of FLM.
FTE4 0 0 0 0 0 : 1 FTE3 0 0 0 0 0 : 1 FTE2 0 0 0 0 1 : 1 FTE1 0 0 1 1 0 : 1 FTE0 0 1 0 1 0 : 1 FLM rising position 0 clock 0.5 clock 1.0 clock 1.5 clock 2.0 clock : 15.5 clcok
Note) Number of clock is the setting value of DIVE1 - 0 of external display interface (2). Numbers in the above chart show the rising position of FLM signal from 0 clock when setting SFTCLK rising point on 0 clock.
FWE7 0 0 0 0 0 0 0 0 : : 1
FWE6 0 0 0 0 0 0 0 0 : : 1
FWE5 0 0 0 0 0 0 0 0 : : 1
FWE4 0 0 0 0 0 0 0 0 : : 1
FWE3 0 0 0 0 0 0 0 0 : : 1
FWE2 0 0 0 0 1 1 1 1 : : 1
FWE1 0 0 1 1 0 0 1 1 : : 1
FWE0 0 1 0 1 0 1 0 1 : : 1
FLM "High" period 0 clock 0.5 clock 1 clock 1.5 clock 2 clock 2.5 clock 3 clock 3.5 clock : : 127.5 clock
Note) Number of clock is the setting value of DIVE1 - 0 of external display interface (2).
Rev.1.11, Oct. 02.2003, page 57 of 175
HD66776 LTPS Interface Control (8) (R017h)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
SWE SWE SWE SWE SWE SWE 3 2 7 6 5 4
SWE 1
SWE 0
0
0
0
STE 4
STE 3
STE 2
STE 1
STE 0
STE4-0: Defines the rising position of SFTCLK1, 2. SWE7-0: Sets the "High" width of SFTCLK1, 2.
STE4 0 0 0 0 0 : 1 STE3 0 0 0 0 0 : 1 STE2 0 0 0 0 1 : 1 STE1 0 0 1 1 0 : 1 STE0 0 1 0 1 0 : 1 SFTCLK rising position 0 clock 0.5 clock 1.0 clock 1.5 clock 2.0 clock : 15.5 clcok
Note) Numbers in the above chart is the clocks from the reference point. The reference point is the rising point when setting SFTCLK rising point on 0 clock.
SWE7 0 0 0 0 0 0 0 0 : : 1
SWE6 0 0 0 0 0 0 0 0 : : 1
SWE5 0 0 0 0 0 0 0 0 : : 1
SWE4 0 0 0 0 0 0 0 0 : : 1
SWE3 0 0 0 0 0 0 0 0 : : 1
SWE2 0 0 0 0 1 1 1 1 : : 1
SWE1 0 0 1 1 0 0 1 1 : : 1
SWE0 0 1 0 1 0 1 0 1 : : 1
SFTCLK "High" period 0 clock 0.5 clock 1 clock 1.5 clock 2 clock 2.5 clock 3 clock 3.5 clock : : 127.5 clock
Note) Number of clock is the setting value of DIVE1 - 0 of external display interface (2).
Rev.1.11, Oct. 02.2003, page 58 of 175
HD66776 LTPS Interface Control (9) (R018h)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
0
0
CLWE CLWECLWE CLWE CLWE CLWE 3 2 1 0 5 4
0
0
0
CLTE CLTE CLTE CLTE CLTE 2 1 0 4 3
CLTE4-0: Defines the CLA rising position. CLWE5-0: Sets the "High" width of CLA/B/C.
CLTE4 0 0 0 0 0 : 1
CLTE3 0 0 0 0 0 : 1
CLTE2 0 0 0 0 1 : 1
CLTE1 0 0 1 1 0 : 1
CLTE0 0 1 0 1 0 : 1
CLA rising position 0 clock 0.5 clock 1.0 clock 1.5 clock 2.0 clock : 15.5 clcok
Note) Numbers in the above chart is the clocks from the reference point. The reference point is the rising point when setting SFTCLK rising point on 0 clock.
CLWE5 0 0 0 0 0 0 0 0 : : 1
CLWE4 0 0 0 0 0 0 0 0 : : 1
CLWE3 0 0 0 0 0 0 0 0 : : 1
CLWE2 0 0 0 0 1 1 1 1 : : 1
CLWE1 0 0 1 1 0 0 1 1 : : 1
CLWE0 0 1 0 1 0 1 0 1 : : 1
CLA/B/C "High" period 0 clock 0.5 clock 1 clock 1.5 clock 2 clock 2.5 clock 3 clock 3.5 clock : : 31.5 clock
Note) Number of clock is the setting value of DIVE1 - 0 of external display interface (2).
Rev.1.11, Oct. 02.2003, page 59 of 175
HD66776 LTPS Interface Control (10) (R019h)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
DPWE DPWE DPWE DPWE DPWE DPWE DPWE DPWE 7 6 5 4 3 2 1 0
0
0
0
DPTE DPTE DPTE DPTE DPTE 4 3 2 1 0
DPTE4-0: Defines the DISPTMG rising position. DPWE7-0: Sets the "High" width of DISPTMG.
DPTE4 0 0 0 0 0 : 1 DPTE3 0 0 0 0 0 : 1 DPTE2 0 0 0 0 1 : 1 DPTE1 0 0 1 1 0 : 1 DPTE0 0 1 0 1 0 : 1 DISPTMG rising position 0 clock 0.5 clock 1.0 clock 1.5 clock 2.0 clock : 15.5 clcok
Note) Numbers in the above chart is the clocks from the reference point. The reference point is the rising point when setting SFTCLK rising point on 0 clock.
DPWE 7 0 0 0 0 0 0 0 0 : : 1
DPWE 6 0 0 0 0 0 0 0 0 : : 1
DPWE 5 0 0 0 0 0 0 0 0 : : 1
DPWE 4 0 0 0 0 0 0 0 0 : : 1
DPWE 3 0 0 0 0 0 0 0 0 : : 1
DPWE 2 0 0 0 0 1 1 1 1 : : 1
DPWE 1 0 0 1 1 0 0 1 1 : : 1
DPWE 0 0 1 0 1 0 1 0 1 : : 1
DISPTMG "High" period 0 clock 0.5 clock 1 clock 1.5 clock 2 clock 2.5 clock 3 clock 3.5 clock : : 127.5 clock
Note) Number of clock is the setting value of DIVE1 - 0 of external display interface (2).
Rev.1.11, Oct. 02.2003, page 60 of 175
HD66776 LPTS Interface Control (11) (R01Ah)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
0
0
0
0
MCPE MCPE MCPE MCPE 3 2 1 0
0
0
0
0
SHE 3
SHE 2
SHE 1
SHE 0
SHE3-0: Defines the hold time from the falling edge of CLA/B/C source output. MCPE3-0: Sets the changing position of AC signal M.
SHE3 0 0 0 0 0 : 1 SHE2 0 0 0 0 1 : 1 SHE1 0 0 1 1 0 : 1 SHE0 0 1 0 1 0 : 1 Source hold time 0 clock 0.5 clock 1.0 clock 1.5 clock 2.0 clock : 15.5 clcok
Note) Numbers in the above chart is the clocks from the reference point. The reference point is the rising point when setting SFTCLK rising point on 0 clock.
MCPE3 0 0 0 0 0 : : 1
MCPE2 0 0 0 0 1 : : 1
MCPE1 0 0 1 1 0 : : 1
MCPE0 0 1 0 1 0 : : 1
M alternating position 0 clock 0.5 clock 1 clock 1.5 clock 2 clock : : 15.5 clock
Note) Number of clock is the setting value of DIVE1 - 0 of external display interface (2).
Rev.1.11, Oct. 02.2003, page 61 of 175
HD66776 LTPS Interface Control (12) (R01Bh)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
0
0
0
0
EQWE EQWE EQWE EQWE 3 2 1 0
0
0
0
0
EQTE EQTE EQTE EQTE 3 2 1 0
EQTE3-0: Defines the equlize starting position. EQWE3-0: Sets "High" width of EQ.
EQTE3 0 0 0 0 1 : 1 EQTE2 0 0 0 0 1 : 1 EQTE1 0 0 1 1 0 : 1 EQTE0 0 1 0 1 0 : 1 Equalize starting position 0 clock 0.5 clock 1.0 clock 1.5 clock 2.0 clock : 7.5 clcok
Note) Numbers in the above chart is the clocks from the reference point. The reference point is the rising point when setting SFTCLK rising point on 0 clock.
MCPE3 0 0 0 0 0 : : 1
MCPE2 0 0 0 0 1 : : 1
MCPE1 0 0 1 1 0 : : 1
MCPE0 0 1 0 1 0 : : 1
M alternating position 0 clock 0.5 clock 1 clock 1.5 clock 2 clock : : 7.5 clock
Note) Number of clock is the setting value of DIVE1 - 0 of external display interface (2).
Rev.1.11, Oct. 02.2003, page 62 of 175
HD66776 Specification of LTPS panel control signal The following is the timing chart of control signal.
Reference point 1H period Display line OSC1 FLM rising position FLM Reference point Reference point 1H period 1H period Reference point
First line
Second line
FLM "High" width
SFTCLK1 SFTCLK rising position SFTCLK2 M reverse position M Source output CLA CLB CLC DISPTMG EQ rising position EQ EQ "High" width SFTCLK "High" width
R
G
B
R
G
B
R
G
B
CLA rising position CLA "High" width
Delay of source output Delay of source output
CLB "High" width Delay of source output CLC "High" width DISPTMG rising position DISPTMG "High" width
Limitations
Internal clock drive mode (CLTI) + 3 x (CLWI) + 3 x SHI < (RTNI) (STI) + (SWI) < (RTNI) (FTI) + (FWI) < (RTNI) (DPTI) + (DPWI) < (RTNI) Internal clock drive mode (CLTE) + 3 x (CLWE) + 3 x SHE < (RTNE) (STE) + (SWE) < (RTNE) (FTE) + (FEW) < (RTNE) (DPTE) + (DPWE) < (RTNE)
Rev.1.11, Oct. 02.2003, page 63 of 175
HD66776 Power control system instruction Power Control 1 (R100h)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
0
0
0
0
0
0
0
0
0
0
0
0
0
DSTB SLP
STB
SLP: When SLP = "1", the HD66776 enters sleep mode, in which the internal display operations are halted except for the R-C oscillator, thus reducing current consumption. Only serial transfer to a power-supply IC and the following instructions can be executed during sleep mode. (i) Power control (BS2-0, DC2-0, AP2-0, SLP, STB, VC2-0, CAD, VR3-0, VRL3-0, VRH4-0, VCOMG, VDV4-0, and VCM4-0 bits) (ii) Common interface control (TE, IDX) During sleep mode, other GRAM data and instructions cannot be updated, although they are retained. STB: When STB = "1", the HD66776 enters standby mode, in which display operation completely stops, halting the internal R-C oscillator. In addition, no external clock pulses are supplied. For details, see the Standby Mode section. Only the following instructions can be executed during standby mode. (i) Standby mode cancel (STB = "0") (ii)Start oscillation During standby mode, serial transfer to the power-supply IC is not possible. Transfer the data again after standby mode is canceled. DSTB: When DSTB = "1", HD66776 enters deep standby mode. During Deep standby mode, it is more power saving compared to the standby mode, because HD66767switch off the logic power supply dering the standby mode. While it is in deep standby mode, contents of GRAM data and instruction set will be broken. Reset GRAM data and instruction set after deep standby mode is canceled. During deep standby mode, serial transfer to the gate driver is not possible. Transfer the data again after standby mode is canceled. Note: The SLP bit is for setting the power-supply IC. Control based on the bits' values is executed by the common driver. For details, see the data sheet for the power supply IC.
Rev.1.11, Oct. 02.2003, page 64 of 175
HD66776 Power Control 2 (R101h)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W
1
DC4
DC3 SAP2 SAP1 SAP0 BT2
BT1
BT0 DC2
DC1
DC0
AP2
AP1
AP0
0
0
SAP2-0: Adjust the amount of fixed current from the fixed current source in the operational amplifier for the LCD. When the amount of fixed current is large,LCD driving capability increases, and it rises picture quality.. But the current consumption is increased. Adjust the fixed current by considering both the display quality and the current consumption. During operation with no display, when SAP2-0 = 000, the current consumption can be reduced by halting the operational amplifier and step-up circuit operation. SAP Bits
SAP2 0 0 0 0 SAP1 0 0 1 1 SAP0 0 1 0 1 Op-amp Current Halt 0.65 0.80 1.00 SAP2 1 1 1 1 SAP1 0 0 1 1 SAP0 0 1 0 1 Op-amp Current 1.35 1.60 Setting disabled Setting disabled
BT2-0: Switch the output factor for step-up. Adjust scale factor of the step-up circuit to meet the voltage used. Lower amplification of the step-up circuit consumes less current. DC4-3: Sets frequency of step-up clock DCCLK.
DC4 0 0 1 1 DC3 0 1 0 1 DCCLK operation frequency fosc / 4 fosc / 8 fosc / 16 fosc / 32
DC2-0: Select the operating frequency for the step-up circuit. When this frequency is high, the driving ability of the step-up circuit and the display quality are high, but the current consumption is increased. Adjust the frequency by considering both the display quality and the current consumption. AP2-0: Adjust the amount of fixed current from the fixed current source in the operational amplifier for the LCD. When the amount of fixed current is large, the LCD driving ability and the display quality are high, but the current consumption is increased. Adjust the fixed current by considering both the display quality and the current consumption. During operation with no display, when AP2-0 = "000", the current consumption can be reduced by ending the operational amplifier and step-up circuit operation. Note: The BS2-0, DC2-0, and AP2-0 bits are for setting the power-supply IC. Control based on the bits' values in executed by the common driver. For details, see the data sheet for the power supply IC.
Rev.1.11, Oct. 02.2003, page 65 of 175
HD66776 Power Control 3 (R102h) Power Control 4 (R103h) Power Control 5 (R104h) Power Control 6 (R105h)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W W W W
1 1 1 1
0 0 0 0
0 0 0 0
0 0 0
0 0 0
0 0
VGL4 VGL3 VGL2 VGL1 VGL0 0 0 0 0 0 0 0 0 0
0 0 0 0
VGH4 VGH3 VGH2 VGH1 VGH0 0 0 VC2 VC1 VC0
VRL3 VRL2 VRL1 VRL0
PON VRH3 VRH2 VRH1 VRH0 VCM4 VCM3 VCM2 VCM1 VCM0
VCO VDV4 VDV3 VDV2 VDV1 VDV0 MG
VGH4-0: Sets the output level of VGH regulator. It is possible to set 2.82 times to 4.06 times REGP voltage. VGL4-0: Sets the output level of VGL regulator. It is possible to set -2.26 times to -4.0 times REGP voltage. VC2-0: Adjust VciOUT output and VREG1OUT input on the basis of Vci. VRL3: When VRL3 ="0", sets PON, VRH3-0, and VC2-0 for HD667P20. When VRL3-0 = "1", sets DK0 for HD667P20. VRL2: Transferred to a power supply IC. VRL2 is not used in HD667P20. VRL1: Transferred to a power supply IC. VRL2 is not used in HD667P20. VRL0: Assigned to DK0 when VRL3=1. PON: Set operation/stop of VLOUT3. PON = 0 is to stop and PON = 1 is to start operation. VRH3-0: Sets an amplification factor for VREG1OUT. The amplification factor can be set to 1.25 to 1.90 times the REGP input. VCOMG: When VCOMG = "1", instruction (VDV) becomes valid because output level of VcomL can be set to any level. VCOMG = "1" is valid when PON = "1". When VCOMG = "0", VcomL is at GND level and setting for instruction (VDV) becomes invalid. When VCOMG = "0", output of VLOUT 4, a power supply for Vcoml, stops. Set VCOMG according to the sequence of a power supply setting flow because VCOMG setting is related to the power supply starting sequence. VDV4-0: Sets amplification factors for Vcom and Vgoff while Vcom AC drive is being performed. The amplification factors can be set to 0.6 to 1.25 times the VREG1 input. When Vcom AC drive is not performed, the settings are invalid. VCM4-0: Sets the VcomH voltage, which is positive when Vcom AC drive is being performed. The amplification factor can be set to 0.41 to 1.00 times the VREG1 input. Setting VCM4-0 to "1" stops the internal resistor adjustment, and the external resistor connected to VcomR can be used to adjust VcomH. Note: The VGH4-0, VGL4-0, VC2-0, PON, VRH3-0, VCOMG, VDV4-0, and VCM4-0 bits are for the power supply IC. Control according to the bits' values is executed by the power-supply IC. for details, see the data sheet for the power-supply IC.
Rev.1.11, Oct. 02.2003, page 66 of 175
HD66776 RAM access system instruction RAM Address Set (R200h) RAM Address Set (R201h)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W W
1 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0
AD7
AD6 AD14
AD5 AD13
AD4
AD3
AD2
AD1 AD9
AD0 AD8
AD16 AD15
AD12 AD11 AD10
AD16-0: Initially set GRAM addresses to the address counter (AC). Once the GRAM data is written, the AC is automatically updated according to the AM and I/D bit settings. This allows consecutive accesses without resetting the addresses. Once the GRAM data is read, the AC is not automatically updated. GRAM address setting is not allowed in standby mode. Ensure that the address is set within the specified window address. When RGB-I/F is in use (RM = "1"), AD16-0 will be set at the falling edge of the VSYNC signal. When the internal clock operation and VSYNC-I/F (RM = "0") are in use, AD16-0 will be set upon execution of an instruction. GRAM Address Range
AD16-AD0 "00000"H - "000FF"H "00100"H - "001FF"H "00200"H - "002FF"H "00300"H - "003FF"H : "13C00"H - "13CFF"H "13D00"H - "13DFF"H "13E00"H - "13EFF"H "13F00"H - "13FFF"H GRAM Setting Bitmap data for Line 1 Bitmap data for Line 2 Bitmap data for Line 3 Bitmap data for Line 4 : Bitmap data for Line 317 Bitmap data for Line 318 Bitmap data for Line 319 Bitmap data for Line 320
Rev.1.11, Oct. 02.2003, page 67 of 175
HD66776 Write Data to GRAM (R202h)
R/W RS W 1 RAM write data (WD17-0). The pin assignment for DB17-0 varies for each interface (see below) PD17 PD16 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Whe RGB- WD I/F is in use
17
WD 16
WD 15
WD 14
WD 13
WD 12
WD 11
WD 10
WD 9
WD 8
WD 7
WD 6
WD 5
WD 4
WD 3
WD 2
WD 1
WD 0
WD17-10: GRAM data is expanded to 18 bits to be written. Please keep in mind that the expansion format varies for each interface. The grayscale level is determined by the GRAM data. The address is automatically updated by the bits of AM and I/D after GRAM writing. GRAM cannot be accessed in standby mode. When the 8- or 16-bit interface is in use, the write data is expanded to 18 bits by writing the MSB of the RB data to its LSB. When data is written to RAM used by RGB-I/F via the system interface, please make sure that write data conflicts do not occur. When the 18-bit RGB-I/F is in use, 18-bit data is written to RAM via PD17-0 and 262,144 colors are available. When the 16-bit RGB-I/F is in use, the MSB is written to its LSB and 65,536 colors are available.
18-bit interface (262,144 colors available)
Input pin
DB DB 17 16
DB 15
DB 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB 8
DB DB 7 6
DB 5
DB 4
DB 3
DB 2
DB 1
DB 0
Write Data to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 17 16 15 14 13 12 11 10 9 8 0 7 6 5 4 3 2 1
RGB Assignment
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
16-bit interface (65,536 colors available)
Input pin DB 17 DB 16 DB DB 15 14 DB DB 13 12 DB 11 DB 10 DB 8 DB 7 DB DB 6 5 DB 4 DB DB 3 2 DB 1
Write Data to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB Assignment
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
Rev.1.11, Oct. 02.2003, page 68 of 175
HD66776
9-bit interface (262,144 colors available)
First transfer (Upper) Input pin DB DB 17 16 DB DB 15 14 DB 13 DB DB 12 11 DB DB DB 10 9 8 Second transfer (Lower) DB DB 7 6 DB 5 DB 4 DB 3 DB DB 2 1 DB 0
Write Data to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB Assignment
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
8-bit interface (1) (65,536 colors available)
First transfer (Upper) Input pin DB DB 17 16 DB DB 15 14 DB 13 DB DB 12 11 DB 10 DB DB 17 16 Second transfer (Lower) DB DB DB 15 14 13 DB DB DB 12 11 10
Write Data to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10
RGB Assignment
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
one pixel
Rev.1.11, Oct. 02.2003, page 69 of 175
HD66776
8-bit interfacer (2) (262,144 colors available)
First transfer Input pin DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 11 10 17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10 Second transfer Third transfer
Write Data to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB Assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
8-bit interfacer (3) (262,144 colors available)
First transfer Input pin DB DB DB DB DB DB 17 16 15 14 13 12 Second transfer DB DB DB DB DB DB 17 16 15 14 13 12 Third transfer DB DB DB DB DB DB 17 16 15 14 13 12
Write Data to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB Assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
Rev.1.11, Oct. 02.2003, page 70 of 175
HD66776
18-bit RGB interface (262,144 colcors available)
Input pin PD PD PD PD PD PD 17 16 15 14 13 12 PD 11 PD 10 PD PD 9 8 PD PD 7 6 PD 5 PD 4 PD 3 PD 2 PD 1 PD 0
Write Data to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
RGB Assignment
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel The index register should be set when data for display is written in RGB-I/F.
16-bit RGB interface (65,536 colcors available)
Input pin PD PD PD PD PD 17 16 15 14 13 PD PD 11 10 PD PD 9 8 PD PD PD 7 6 5 PD PD 4 3 PD PD 2 1
Write Data to GRAM
WD WD WD WD WD 17 16 15 14 13
WD WD WD WD WD WD WD WD WD WD WD 11 10 9 8 7 6 5 1 4 3 2
RGB Assignment
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel The index register should be set when data for display is written in RGB-I/F.
6-bit RGB interface (262,144 colcors available)
First transfer Input pin PD PD PD 17 16 15 Second transfer PD PD 15 14 PD PD 13 12 PD 17 Third transfer PD PD 16 15 PD PD 14 13 PD 12
PD PD PD PD PD 14 13 12 17 16
Write Data to GRAM
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 0 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
RGB Assignment
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel The index register should be set when data for display is written in RGB-I/F.
Rev.1.11, Oct. 02.2003, page 71 of 175
HD66776 GRAM Data and LCD Output REV = 0
GRAM Data Setting RGB 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 Grayscale Polarity Negative V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 Positive V63 V62 V61 V60 V59 V58 V57 V56 V55 V54 V53 V52 V51 V50 V49 V48 V47 V46 V45 V44 V43 V42 V41 V40 V39 V38 V37 V36 V35 V34 V33 V32 GRAM Data Setting RGB 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 Grayscale Polarity Negative V32 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 V43 V44 V45 V46 V47 V48 V49 V50 V51 V52 V53 V54 V55 V56 V57 V58 V59 V60 V61 V62 V63 Positive V31 V30 V29 V28 V27 V26 V25 V24 V23 V22 V21 V20 V19 V18 V17 V16 V15 V14 V13 V12 V11 V10 V9 V8 V7 V6 V5 V4 V3 V2 V1 V0
Rev.1.11, Oct. 02.2003, page 72 of 175
HD66776 REV = 1
GRAM Data Setting RGB 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 011010 011011 011100 011101 011110 011111 Grayscale Polarity Negative V63 V62 V61 V60 V59 V58 V57 V56 V55 V54 V53 V52 V51 V50 V49 V48 V47 V46 V45 V44 V43 V42 V41 V40 V39 V38 V37 V36 V35 V34 V33 V32 Positive V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 GRAM Data Setting RGB 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 111000 111001 111010 111011 111100 111101 111110 111111 Grayscale Polarity Negative V31 V30 V29 V28 V27 V26 V25 V24 V23 V22 V21 V20 V19 V18 V17 V16 V15 V14 V13 V12 V11 V10 V9 V8 V7 V6 V5 V4 V3 V2 V1 V0 Positive V32 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 V43 V44 V45 V46 V47 V48 V49 V50 V51 V52 V53 V54 V55 V56 V57 V58 V59 V60 V61 V62 V63
Rev.1.11, Oct. 02.2003, page 73 of 175
HD66776 RAM Access via RGB-I/F and System I/F All the data for display is written to the internal RAM in the HD66776 when RGB-I/F is in use. In this method, data, including that in both the moving picture area and the screen update frame, can only be transferred via RGB-I/F. In addition to using the high-speed write mode (HWM1-0 = "11") and the window address function, the power consumption can be reduced and high-speed access can be achieved while moving pictures are being displayed. Data for display that is not in the moving picture area or the screen update frame can be rewritten via the system interface. RAM can be accessed via the system interface when RGB-I/F is in use. When data is written to RAM during RGB-I/F mode, the ENABLE bit should be high to stop data writing via RGB-I/F, because RAM writing is always performed in synchronization with the DOTCLK input when ENABLE is low. After this RAM access via the system interface, a waiting time is needed for a write/read bus cycle before the next RAM access starts via RGB-I/F. When a RAM write conflict occurs, data writing is not guaranteed.
Updating Updating
VSYNC ENABLE DOTCLK PD17-0
Setting of index System interface Index R202 Updating or moving picture area RM=0 Setting Index of R202 address Updating of area other than moving picture area RM=1 Setting of address Index R202 Updating or moving picture area
U p d a ti n g o f s t i l l p i c t u r e area*1
Note 1: When RGB-I/F is in use, an address is set at every falling edge of VSYNC. 2: An address and an index (R202h) should be set before RAM is accessed via RGB-I/F. 3: The high-speed write mode (HWM1-0 = "11") should be used in RGB-I/F and VSYNC-I/F.
2001/01/01 00:00 Still picture area
Moving picture area
Example of Updating Still Picture Area during Diaplaying Moving Picture
Rev.1.11, Oct. 02.2003, page 74 of 175
HD66776 Read Data from GRAM (R203h)
R/W RS R 1
RAM read data (RD17-0) The pin assignment for DB17-0 varies for eachinterface (see below).
RD17-0: Read 18-bit data from GRAM. When the data is read to the microcomputer, the first-word read immediately after the GRAM address setting is latched from the GRAM to the internal read-data latch. The data in the data bus (DB17-0) becomes invalid and the second-word read is normal. When bit processing, such as a logical operation, is performed by the HD66776, only one read can be processed since the latched data in the first word is used. Please make sure bit processing is performed in 18-bit units. When the 8-/16bit interface is in use, the LSB of RB write data will not be read. When RGB-I/F is in use, this function is not available.
18-bit interface
GRAM data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
One pixel
Read data RD RD RD RD 17 16 15 14
RD RD RD RD RD RD RD 13 12 11 10 9 8 7
RD RD RD RD 6 5 4 3
RD RD RD 2 1 0
Output
DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
DB 9
DB DB 8 7
DB 6
DB 5
DB DB 4 3
DB 2
DB 1
DB 0
16-bit interface
GRAM data R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
One pixel
Read data
RD RD RD RD 17 16 15 14
RD RD RD RD RD RD RD 13 12 11 10 9 8 7
RD RD RD RD 6 5 4 3
RD RD RD 0 2 1
Output
DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
DB 8
DB 7
DB DB 6 5
DB 4
DB 3
DB 2
DB 1
Rev.1.11, Oct. 02.2003, page 75 of 175
HD66776
9-bit interface
GRAM data
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
GRAM data RD RD RD RD Read data 17 16 15 14
RD RD RD RD RD RD RD 13 12 11 10 9 8 7
One pixel
RD RD RD RD 6 5 4 3
RD RD RD 2 1 0
Output
DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
DB DB 9 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
DB 9
First transfer (Upper)
Second transfer (Lower)
8-bit interface / SPI
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Read data
RD RD RD RD 17 16 15 14
RD RD RD RD RD RD RD 13 12 11 10 9 8 7
RD RD RD RD 6 5 4 3
RD RD RD 0 2 1
Output
DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
DB 17
DB 16
DB DB 15 14
DB 13
DB 12
DB 11
DB 10
First transfer (Upper)
Second transfer (Lower)
Rev.1.11, Oct. 02.2003, page 76 of 175
HD66776
Sets the I/D, AM, HAS/HSE, and VSA/VEA bits
Address: N set
First word
Dummy read (invalid data) GRAM->Read-data latch
Second word
Read (data of address n) Read-data latch-> DB17-0
Address: M set
First word
Dummy read (invalid data) GRAM->Read-data latch
Second word
Read (data of address n) Read-data latch-> DB17-0
i) Data read to the microcomputer
GRAM read sequence
Rev.1.11, Oct. 02.2003, page 77 of 175
HD66776 RAM Write Data Mask (R203h) RAM Write Data Mask (R204h)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W W
1 1
0 0
0 0
WM 11 0
WM 10 0
WM 9 0
WM 8 1
WM 7 1
WM 6 1
0 0
0 1
WM 5 WM 17
WM 4 WM 16
WM 3 WM 15
WM 2 WM 14
WM 1 WM 13
WM 0 WM 12
WM17-0: In writing to GRAM, these bits mask the writing in a bit unit. When WM17 = "1", this bit masks the MSB of the write data and does not write to GRAM. Similarly, the WM16-0 bits mask the data written to GRAM in a bit unit. For details, see the Graphics Operation Function section. Please make sure the write data to GRAM (18-bit data) is masked. When RGB-I/F is in use, this function is not available.
Write mask
WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM WM 9 8 7 6 5 4 3 2 1 0 17 16 15 14 13 12 11 10
Wrote data to GRRAM
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Rev.1.11, Oct. 02.2003, page 78 of 175
HD66776 Control Instructions Control (R300h to R309h)
R/W R300 R301 R302 R303 R304 R305 R306 R307 R308 R309 W W W W W W W W W W RS 1 1 1 1 1 1 1 1 1 1 IB15 IB14 IB13 IB12 IB1 BI10 IB9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB8 IB7 0 0 0 0 0 0 0 0 0 0 IB6 0 0 0 0 0 0 0 0 0 0 IB5 0 0 0 0 0 0 0 0 0 0 IB4 0 0 0 0 0 0 0 0 0 0 IB3 0 0 0 0 IB2 IB1 IB0
PKP PKP PKP 12 11 10 PKP PKP PKP 32 31 30 PKP PKP PKP 52 51 50 PRP PRP PRP 12 11 10
PKP PKP PKP 02 01 00 PKP PKP PKP 22 21 20 PKP PKP PKP 42 41 40 PRP PRP PRP 02 01 00
VRP VRP VRP VRP VRP 14 13 12 11 10 0 0 0 0 0 0 0 0 PKN PKN PKN 12 11 10 PKN PKN PKIN 32 31 30 PKN PKN PKN 52 51 50 PRN PRN PRN 12 11 10
VRP VRP VRP VRP 03 2 01 00 0 0 0 0 PKN PKN PKN 02 01 00 PKN PKN PKN 22 21 20 PKN PKN PKN 42 41 40 PRN PRN PRN 02 01 00
VRN VRN VRN VRN VRN 14 13 12 11 10
VRN VRN VRN VRN 03 02 01 00
PKP52-00: The fine adjustment registers for positive polarity PRP12-00: The gradient adjustment registers for positive polarity VRP14-00: The amplitude adjustment registers for positive polarity PKN42-00: The fine adjustment registers for negative polarity PRN12-00: The gradient adjustment registers for negative polarity VRN14-00: The amplitude adjustment registers for negative polarity For details, see the section on the adjustment.
Rev.1.11, Oct. 02.2003, page 79 of 175
HD66776 Position Control Instructions Vertical Scroll Control (R400h) Vertical Scroll Control (R401h)
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
W W
1 1
0 0
0 0
0 0
0 0
0 0
0 0
0 0
VL18
VL17
VL16 VL26
VL15 VL25
VL14 VL13 VL12 VL11 VL10 VL24 VL23 VL22 VL21 VL20
VL28 VL27
VL18-10: Specify the amount of scroll in the display to enable smooth vertical scrolling. Any raster-row from 0 to 319 can be displayed with scrolling. After the 320th raster-row is displayed, the display restarts from the 1st raster-row. The display-start raster-row (VL18-10) is valid only when VLE1 = "1" or VLE2 = "1". The raster-row display is fixed when VLE1 = "0". *: When the external display interface is in use, this function is not available. VL Bits and Display-start Raster-row
VL18 0 0 0 : 1 1 VL17 0 0 0 : 0 0 VL16 0 0 0 : 0 0 VL15 0 0 0 : 1 1 VL14 0 0 0 : 1 1 VL13 0 0 0 : 1 1 VL12 0 0 0 : 1 1 VL11 0 0 1 : 1 1 VL10 0 1 0 : 0 1 Amount of Scrolling (Number of raster-row) Line 0 Line 1 Line 2 : Line 318 Line 319
Note: Do not set to over 319 ("13F"H) raster-rows.
VL28-20: Specify the amount of scroll in the 2nd display to enable smooth vertical scrolling. Any rasterrow from 0 to 319 can be displayed with scrolling. After the 320th raster-row is displayed, the display restarts from the 1st raster-row. The display-start raster-row (VL28-20) is valid only when VLE2 = "1". The raster-row display is fixed when VLE2 = "0". *: When the external display interface is in use, this function is not available. VL Bits and Display-start Raster-row
VL28 0 0 0 : 1 1 VL27 0 0 0 : 0 0 VL26 0 0 0 : 0 0 VL25 0 0 0 : 1 1 VL24 0 0 0 : 1 1 VL23 0 0 0 : 1 1 VL22 0 0 0 : 1 1 VL21 0 0 1 : 1 1 VL20 0 1 0 : 0 1 Amount of Scrolling (Number of raster-row) Line 0 Line 1 Line 2 : Line 318 Line 319
Note: Do not set to over 319 ("13F"H) raster-rows.
Rev.1.11, Oct. 02.2003, page 80 of 175
HD66776 1st-screen driving position (1) (R402h) 1st-screen driving position (2) (R403h) 2nd-screen driving position (1) (R404h) 2nd-screen driving position (2) (R405h)
R/W W W W W RS 1 1 1 1 IB15 IB14 IB13 IB12 IB1 BI10 IB9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB8 SS 18 SE 18 SS 28 SE 28 IB7 SS 17 SE 17 SS 27 SE 27 IB6 SS 16 SE 16 SS 26 SE 26 IB5 SS 15 SE 15 SS 25 SE 25 IB4 SS 14 SE 14 SS 24 SE 24 IB3 SS 13 SE 13 SS 23 SE 23 IB2 SS 12 SE 12 SS 22 SE 22 IB1 SS 11 SE 11 SS 21 SE 21 IB0 SS 10 SE 10 SS 20 SE 20
SS18-0: Specify the driving start position for the first screen in a line unit. The LCD driving starts from the 'set value + 1' gate driver. SE18-0: Specify the driving end position for the first screen in a line unit. The LCD driving is performed to the 'set value + 1' gate driver. For instance, when SS18-10 = "07"H and SE18-10 = "10"H are set, the LCD driving is performed from G8 to G17, and non-selection driving is performed for G1 to G7, G18, and others. Ensure that SS18-10 SE18-10 "13F"H. For details, see the Screen-division Driving Function section. SS28-0: Specify the driving start position for the second screen in a line unit. The LCD driving starts from the 'set value + 1' gate driver. The second screen drives when SPT = "1". SE28-0: Specify the driving end position for the second screen in a line unit. The LCD driving is performed to the 'set value + 1' gate driver. For instance, when SPT = "1", SS28-20 = "20"H, and SE28-20 = "4F"H are set, the LCD driving is performed from G33 to G80. Ensure that SS18-10 SE18-10 < SS2820 SE28-20 "13F"H. For details, see the Screen-division Driving Function section.
Rev.1.11, Oct. 02.2003, page 81 of 175
HD66776 Horizontal RAM address position (R406h) Vertical RAM address position (R407h) Horizontal RAM address position (R408h) Vertical RAM address position (R409h)
R/W W W W W RS 1 1 1 1 IB15 IB14 IB13 IB12 IB1 BI10 IB9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IB8 0 0 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0
HSA HSA HSA HSA HSA HSA HSA HSA 7 6 5 4 3 2 1 0 HEA HEA HEA HEA HEA HEA HEA HEA 7 6 5 4 3 2 1 0
VSA VSA VSA VSA VSA VSA VSA VSA VSA 8 7 6 5 4 3 2 1 0 VEA VEA VEA VEA VEA VEA VEA VEA VEA 8 7 6 5 4 3 2 1 0
HSA7-0/HEA7-0: Specify the horizontal start/end positions of a window for access in memory. Data can be written to the GRAM from the address specified by HEA7-0 from the address specified by HSA7-0. Note that an address must be set before RAM is written to. Ensure 00h HSA7-0 HEA7-0 "FF"h. VSA8-0/VEA8-0: Specify the vertical start/end positions of a window for access in memory. Data can be written to the GRAM from the address specified by VEA8-0 from the address specified by VSA8-0. Note that an address must be set before RAM is written to. Ensure "000"h VSA8-0 VEA8-0 "13F"h.
HSA
00000h
HEA
VSA
Window Address
Window address setting area "00"h <= HSA7-0 <= HEA7-0 <= "FF"h "000"h <= VSA8-0 <= VEA8-0 <= "13E"h
VEA
GRAM address space
13FFFh
Note: Ensure that the window address area is within the GRAM address space.
Rev.1.11, Oct. 02.2003, page 82 of 175
HD66776
Instruction List
Major Division Index u pper Index SR Status read 0** Display control Index 000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Fn 020h-0FFh 1* * Power control 100h 101h 102h 103h 104h 105h 107h-1FFh 2** RAM access 200h 201h 202h 203h 204h 205h-2FFh 3** control 300h 301h 302h 303h 304h 305h 306h 307h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh 30Fh 310h-3FFh Coordinate control 400h 401h 402h 403h 404h 405h 406h 407h 408h 409h 5* * 6* * 7* * F* * 40Ah-4FFh * * * * Minor Division Command Index Status read Display control Device code read Driver output control LCD drive AC control Entry mode Setting inhibited Setting inhibited Setting inhibited Display control (1) Display control (2) Setting inhibited Power supply IC interface control Settin inhibited g External display interface control (1) 0 Frame frequency adjustment control 0 External display interace control (2) 0 0 0 0 0 0 0 0 0 0 FWI5 (0) 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVI1 (0) DIVE1 (1) 0 DM1 DM0 RIM1 RIM0 RM 0 0 0 0 (0) (0) (0) (0) (0) DIVI0 RTNI4 RTNI3 RTNI2 RTNI1 RTNI0 0 0 0 (1) (0) (0) (0) (0) (1) DIVE0 RTNE RTNE RTNE5 RTNE4 RTNE3 RTNE2 RTNE1 RTNE0 (0) 7 (0) 6 (0) (0) (1) (1) (1) (1) (0) VSPL HSPL VPL EPL DPL 0 0 0 0 (0) (0) (0) (0) (0) FWI0 FT2 FT1 FT0 0 0 0 0 0 (0) (0) (0) (0) SWI0 STI2 STI1 STI0 0 0 0 0 0 (0) (0) (0) (0) CLTI3 CLTI2 CLTI1 CLTI0 CLWI0 0 0 0 0 (0) (0) (0) (0) (0) DPTI2 DPTI1 DPTI0 DPWI0 0 0 0 0 0 (0) (0) (0) (0) MCPI0 SHI1 SHI0 0 0 0 0 0 0 (0) (0) (0) EQWI0 EQTI2 EQTI1 EQTI0 0 0 0 0 0 (0) (0) (0) (0) FWE0 FTE4 FTE3 FTE2 FTE1 FTE0 0 0 0 (0) (0) (0) (0) (0) (0) STE4 STE3 STE2 STE1 STE0 SWE0 0 0 0 (0) (0) (0) (0) (0) (0) CLWE0 CLTE4 CLTE3 CLTE2 CLTE1 CLTE0 0 0 0 (0) (0) (0) (0) (0) (0) DPWE0 DPTE4 DPTE3 DPTE2 DPTE1 DPTE0 0 0 0 (0) (0) (0) (0) (0) (0) MCPE0 SHE3 SHE2 SHE1 SHE0 0 0 0 0 (0) (0) (0) (0) (0) EQWE0 EQTE3 EQTE2 EQTE1 EQTE0 0 0 0 0 (0) (0) (0) (0) (0) 0 0 0 0 0 0 0 0 0 0 BT0 (0) 0 VRL0 (0) VDV0 (0) 0 0 DC2 (0) 0 0 0 0 DC1 (0) 0 0 0 0 DC0 (0) 0 0 0 0 AP2 (0) 0 0 AP1 (0) 0 DSTB (0) AP0 (0) SLP (0) 0 STB (0) 0 0 0 0 0 0 0 0 TE (0) 0 0 0 0 0 IDX2 (0) IDX1 (0) IDX0 (0) COL (0) 0 0 0 0 0 0 0 0 FP3 (1) VLE2 (0) FP2 (0) VLE1 (0) FP1 (0) SPT (0) FP0 (0) PT1 (0) 0 PT0 (0) 0 GON (0) 0 DTE (0) 0 0 BP3 (1) REV (0) BP2 (0) D1 (0) BP1 (0) D0 (0) BP0 (0) IB15 * 0 * 0 0 0 0 IB14 * 0 * 0 0 0 0 IB13 * 0 * 0 0 0 0 Upper code IB12 IB11 * ID11 0 0 * * 0 0 0 0 BGR (0) 0 0 0 IB10 ID10 0 * 1 0 0 0 IB8 ID8 L8 * 1 SS 0 (0) B/O EOR (0) (0) HWM1 HWM0 (0) (0) IB9 ID9 0 * 1 IB7 ID7 L7 * 0 0 0 0 IB6 ID6 L6 * 1 0 0 0 IB5 ID5 L5 * 1 NL5 (1) NW5 (0) ID1 (1) Lower code IB4 IB3 ID4 ID3 L4 L3 * * 1 0 NL4 NL3 (0) (0) NW4 NW3 (0) (0) ID0 AM (1) (0) Note IB2 ID2 L2 * 1 NL2 (1) NW2 (0) LG2 (0) IB1 ID1 L1 * 1 NL1 (1) NW1 (0) LG1 (0) IB0 ID0 L0 1 0 NL0 (1) NW0 (0) LG0 (0)
External desplay interface control (3) 0 lTP interface control (1) LTPS interace control (2) LTPS interface control (3) LTPS interface control (4) LTPS interface control (5) LTPS interface control (6) LTPS interface control (7) LTPS interface control (8) LTPS interface control (9) LTPS interface control (10) LTPS interface control (11) LTPS interface control (12) LTPS interface control (13) Setting inhibited Power control (1) Power control (2) Setting inhibited Power control (4) Power control (5) Power control (6) Settin inhibited g RAM address set (1) RAM address set (2) RAM data write/read RAM write data mask (1) RAM write data mask (2) Settin inhibited g control (1) control (2) control (3) control (4) control (5) control (6) control (7) control (8) control (9) control (10) Settin inhibited g Settin inhibited g Settin inhibited g Settin inhibited g g Settin inhibited g Settin inhibited Settin inhibited g Vertical scroll control (1) Vertical scroll control (2) Frist screen driving position (1) Frist screen driving position (2) Second screen driving position (1) Second screen driving position (2) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FWI4 FWI3 FWI2 FWI1 (0) (0) (0) (0) SWI5 SWI4 SWI4 SWI2 SWI1 0 0 (0) (0) (0) (0) (0) CLWI4 CLWI3 CLWI2 CLWI1 0 0 0 (0) (0) (0) (0) DPWI4 DPWI3 DPWI2 DPWI1 0 0 DPWI5 (0) (0) (0) (0) (0) MCPI2 MCPI1 0 0 0 0 0 (0) (0) EQWI1 0 0 0 0 0 0 (0) FWE7 FWE6 FWE4 FWE3 FWE2 FWE1 FWE5 (0) (0) (0) (0) (0) (0) (0) SWE7 SWE6 SWE4 SWE3 SWE2 SWE1 SWE5 (0) (0) (0) (0) (0) (0) (0) CLWE5 CLWE4 ClWE3 CLWE2 CLWE1 0 0 (0) (0) (0) (0) (0) DPWE7 DPWE6 DPWE5 DPWE4 DPWE3 DPWE2 DPWE1 (0) (0) (0) (0) (0) (0) (0) MCPE3 MCPE2 MCPE1 0 0 0 0 (0) (0) (0) EQWE3 EQWE2 EQWE1 0 0 0 0 (0) (0) (0) 0 0 0 0 0 0 0 0 DC4 (0) 0 DC3 (0) 0 SAP2 (0) 0 0 VCOMG (0) 0 0 SAP1 (0) 0 0 VDV4 (0) 0 0 SAP0 (0) 0 VRL3 (0) VDV3 (0) 0 0 BT2 (0) 0 VRL2 (0) VDV2 (0) 0 0 BT1 (0) 0 VRL1 (0) VDV1 (0) 0
0 0 0
VC1 VC0 VC2 (0) (0) (0) PON VRH3 VRH2 VRH1 VRH0 (0) (0) (0) (0) (0) VCM4 VCM3 VCM2 VCM1 VCM0 (0) (0) (0) (0) (0)
AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 (0) (0) (0) (0) (0) (0) (0) (0) AD16 AD15 AD14 AD13 AD12 AD11 A10 AD9 AD8 0 0 0 0 0 0 (0) 0) (0) (0) (0) (0) (0) (0) (0) RAM write data (WD17-0)/RAM read data (RD17-0) *Bit assignment changes according to the selected interface . WM5 WM4 WM3 WM2 WM1 WM0 WM10 WM9 WM8 WM7 WM6 0 WM11 (0) 0 0 (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) WM17 WM16 WM15 WM14 WM13 WM12 0 0 0 0 0 0 0 0 0 (0) (0) (0) (0) (0) (0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKP12 (0) PKP32 (0) PKP52 0 0 (0) PRP12 0 0 (0) VRP14 VRP13 VRP12 (0) (0) (0) PKN12 0 0 (0) PKN32 0 0 (0) PKN52 0 0 (0) PRN12 0 0 (0) VRN14 VRN13 VRN12 (0) (0) (0) 0 0 0 0 PKP11 (0) PKP31 (0) PKP51 (0) PRP11 (0) VRP11 (0) PKN11 (0) PKN31 (0) PKN51 (0) PRN11 (0) VRN11 (0) PKP10 (0) PKP30 (0) PKP50 (0) PRP10 (0) VRP10 (0) PKN10 (0) PKN30 (0) PKN50 (0) PRN10 (0) VRN10 (0) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKP02 PKP01 PKP00 (0) (0) (0) PKP22 PKP21 PKP20 (0) (0) (0) PKP42 PKP41 PKP40 0 (0) (0) (0) PRP02 PRP01 PRP00 0 (0) (0) (0) VRP03 VRP02 VRP01 VRP00 (0) (0) (0) (0) PKN02 PKN01 PKN00 0 (0) (0) (0) PKN22 PKN21 PKN20 0 (0) (0) (0) PKN42 PKN41 PKN40 0 (0) (0) (0) PRN02 PRN01 PRN00 0 (0) (0) (0) VRN03 VRN02 VRN01 VRN00 (0) (0) (0) (0) 0 0
4**
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
VL18 (0) 0 SS18 (0) SE18 (1) SS28 (0) SE28 (1) 0 0 VSA8 (0) VEA8 (1)
Horiozontal RAM address position)(1 0 Horiozontal RAM address position)(2 0 Vertical RAM address position (1) Vertical RAM address position (2) Settin inhibited g Settin inhibited g Settin inhibited g g Settin inhibited Settin inhibited g 0 0
VL17 (0) VL27 (0) SS17 (0) SE17 (1) SS27 (0) SE27 (1) HSA7 (0) HEA7 (1) VSA7 (0) VEA7 (0)
VL16 (0) VL26 (0) SS16 (0) SE16 (1) SS26 (0) SE26 (1) HSA6 (0) HEA6 (1) VSA6 (0) VEA6 (0)
VL15 (0) VL25 (0) SS15 (0) SE15 (1) SS25 (0) SE25 (1) HSA5 (0) HEA5 (1) VSA5 (0) VEA5 (1)
VL14 (0) VL24 (0) SS14 (0) SE14 (1) SS24 (0) SE24 (1) HSA4 (0) HEA4 (0) VSA4 (0) VEA4 (1)
VL13 (0) VL23 (0) SS13 (0) SE13 (1) SS23 (0) SE23 (1) HSA3 (0) HEA3 (1) VSA3 (0) VEA3 (1)
VL12 (0) VL22 (0) SS12 (0) SE12 (1) SS22 (0) SE22 (1) HSA2 (0) HEA2 (1) VSA2 (0) VEA2 (1)
VL11 (0) VL21 (0) SS11 (0) SE11 (1) SS21 (0) SE21 (1) HSA1 (0) HEA1 (1) VSA1 (0) VEA1 (1)
VL10 (0) VL20 (0) SS10 (0) SE10 (1) SS20 (0) SE20 (1) HSA0 (0) HEA0 (1) VSA0 (0) VEA0 (1)
Rev.1.11, Oct. 02.2003, page 83 of 175
HD66776
Reset Function
The HD66776 is internally initialized by RESET input inside the HD66776 is in busy state during the reset period and no instruction or GRAM data access from the MPU is accepted. Reset the power-supply IC as its settings are not automatically reinitialized when the HD66776 is reset. The reset input must be held for at least 1ms. Do not access the GRAM or initially set the instructions until the R-C oscillation frequency is stable after power has been supplied (10ms). Instruction set initialization Indicated in the liwer row of each cell in Table 57. GRAM Data Initialization This is not automatically initialized by reset input but must be initialized by software while display is off (D1-0 = "00"). Output Pin Initialization 1. 2. 3. 4. LCD driver output pins (source outputs): Output GND level Oscillator output pin (OSC2): Outputs oscillation signal Power supply IC interface signals (GCS*, GCL, and GDA): Halt Timing signals: Halt (M, FLM, SFTCLK1, SFTCLK2, CLA, CLB, CLC, DISPTMG, DCCLK, EQ)
Rev.1.11, Oct. 02.2003, page 84 of 175
HD66776
Interface Specifications
The HD66776 incorporates a system interface, which is used to set instructions, and an external display interface, which is used to display moving pictures. Selecting these interfaces to match the screen data (moving or still enables efficient transfer of data for display. The external display interface includes RGB-I/F and VSYNC-I/F. This allows flicker-free screen update. When RGB-I/F is selected, the synchronization signals (VSYNC, HSYNC, and DOTCLK) are available for use in operating the display. The data for display (PD17-0) is written according to the values of the data enable signal (ENABLE) and data valid signal (VLD), in synchronization with the VSYNC, HSYNC, and DOTCLK signals. The data for display is written to GRAM, so that data transfer is reduced only when switching the screen. In addition, using the window address function enables rewriting only to the internal RAM area to display moving pictures. Using this function also enables simultaneously display of the moving picture are and the RAM data that was written. While displaying moving pictures, the data for display should be written in high-speed access via RGB-I/F or VSYNC-I/F. The internal display operation I synchronized with the frame synchronization signal (VSYNC) in VSYNC interface mode. When writing to the internal RAM is done within the required time after the falling edge of VSYNC, moving pictures can be displayed via the conventional interface. There are some limitations on the timing and methods of writing to RAM. See the section on the external display interface. The HD66776has four operation modes for each display state. These settings are specified by control instructions for external display interface. Transitions between modes should follow the transition flow.
Rev.1.11, Oct. 02.2003, page 85 of 175
HD66776 Operation mode and interface
Operation Mode Internal operating clock only (Displaying still picture) RGB interface (1) (Displaying moving picture) RGB interface (2) (Rewriting still picture while displaying moving pictures) VSYNC interface (Displaying moving pictures) Note RAM Access Setting (RM) System interface (RM = 0) RGB interface (RM = 1) System interface (RM = 0) System interface (RM = 0) Display Operation Mode (DM1-0) Internal operating clock (DM1-0 = 00) RGB interface (DM1-0 = 01) RGB interface (DM1-0 = 01) VSYNC interface (DM1-0 = 10)
1:Instruction registers can only be set via system interface. 2:RGB-I/F and VSYNC-I/F cannot be used at the same time. 3:RGB-I/F mode (RIM-0) cannot be set while RGB I/F is operating. 4:For mode transitions see the section on the external display interface. 5:RGB-I/F and VSYNC-I/F modes should be used in high-speed write mode (HWM1-0 = 11).
CSn* RS WR* (RD*) DB17-0 System 18/16/9/8 VLD ENABLE VSYNC HSYNC DOTCLK 18/16/6 PD17-0 HD66776
System interface
RGB interface
Rev.1.11, Oct. 02.2003, page 86 of 175
HD66776
System Interface
The following interfaces are available as sytem interface. It is determined by setting bits of IM3-0. Instructions and RAM accesses can be performed via the system interface. IM bits
IM3 0 0 0 0 0 0 1 1 1 1 1 IM2 0 0 0 0 1 1 0 0 0 0 1 IM1 0 0 1 1 0 1 0 0 1 1 * IM0 0 1 0 1 * * 0 1 0 1 * System Interface Setting disabled Setting disabled 80-system 16-bit interface 80-system 8-bit interface Clocked serial peripheral interface (SPI) Setting disabled Setting disabled Setting disabled 80-system 18-bit interface 80-system 9-bit interface Setting disabled DB17 to 0 DB17 to 9 DB17 to 10 and 8 to 1 DB17 to 10 DB1 to 0 DB Pin
Rev.1.11, Oct. 02.2003, page 87 of 175
HD66776 80-system 18-bit bus interface 80-system 18-bit parallel data transfer can be used by setting IM3/2/1/0 pins to Vcc/GND/Vcc/GND levels.
MPU
CSn* A1 HWR* (RD*) D31-0 18
CSn* RS WR* (RD*) DB17-0
HD66776
Data format for 18-bit interface
Input pin
DB 17
DB DB 16 15
DB 14
DB DB 13 12
DB 11
DB DB 10 9
DB DB DB 8 7 6
DB 5
DB 4
DB DB DB 3 2 1
DB 0
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code
RAM data write
Input pin
DB 17
DB 16
DB 15
DB 14
DB 13
DB 12
DB DB DB 12 10 9
DB 8
DB 7
DB DB 6 5
DB 4
DB 3
DB 2
DB 1
DB 0
GRRA M write R5 data
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
262,144 colors are available in 18-bit system interface.
Rev.1.11, Oct. 02.2003, page 88 of 175
HD66776 80-system 16-bit bus interface 80-system 16-bit parallel data transfer can be used by setting IM3/2/1/0 pins to GND/GND/Vcc/GND levels
CSn* A1 H8/2245 HWR* (RD*) D15-0 16
CSn* RS WR* (RD*)
HD66776
DB17-0, 8-1
Example of interface with 16-bit microcomputer
Data format for 16-bit interface
Instruction Input pin DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code
RAM data write Input pin DB DB DB DB DB DB DB DB
17 16 15 14 13 12 11 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1
GRAM write data
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel 65,536 colors are available in 16-bit system interface.
Rev.1.11, Oct. 02.2003, page 89 of 175
HD66776 80-system 9-bit bus interface 80-system 9-bit parallel data transfer can be used by setting IM3/2/1/0 pins to Vcc/GND/Vcc/Vcc levels. 16-bit instruction is divided into two parts, which are lower and upper, and the upper eight bits are first transferred. The LSB of the bus is not used. RAM data is also divided into two parts, which are lower and upper, and the upper nine bits are first transferred. Unused pins (DB8-0) must be fixed to the Vcc or GND level. Ensure that upper bytes have to be written when writing the index register.
CSn* A1 H8/2245 HWR* (RD*) D15-0 9 9 GND
CSn* RS WR* (RD*) DB17-9 DB8-0
HD66776
Example of interface with 8-bit microcomputer Data format for 8-bit interface (1) Instruction
Input pin DB 17
First transfer
DB DB 16 15 DB DB 14 13 DB 12 DB DB 11 10 DB 9 DB 17 DB 16
Second transfer
DB DB 15 14 DB DB 13 12 DB 11 DB DB 10 9
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code
RAM data write First transfer
Input pin DB DB DB 17 16 15 DB DB 14 13 DB 12 DB DB 11 10 DB 9 DB 17
Second transfer
DB DB DB 16 15 14 DB DB 13 12 DB DB DB 11 10 9
GRAM write data
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
Rev.1.11, Oct. 02.2003, page 90 of 175
HD66776 Note: Transfer synchronization function for 9-bit bus interface. The HD66776 supports the transfer synchronization function, which resets the upper/lower counter to count upper/lower 9-bit data transfer in the 9-bit bus interface. Noise causing transfer mismatch between the nine upper and lower bits can be corrected by a reset triggered by consecutively writing a 00H instruction four times. The next transfer starts from the upper eight bits. Executing synchronization function periodically can recover any runaway in the display system.
RS RD WR DB17-9 Upper/ Lower "00"H (1) "00"H (2) "00"H (3) "00"H (4) Upper Lower
(9-bit transfer synchronization)
Rev.1.11, Oct. 02.2003, page 91 of 175
HD66776 80-system 8-bit bus interface 80-system 8-bit parallel data transfer can be used by setting IM3/2/1/0 pins to GND/GND/Vcc/Vcc levels. 16-bit instruction is divided into two parts, which are lower and upper, and the upper eight bits are first transferred. According to the setting of TRI, RAM data for one word are divided into two or three for two time transfer or three time transfer. The LSB of the bus is not used. RAM data is also divided into two parts, which are lower and upper, and the upper nine bits are first transferred. Data for RAM write is expanded to 18-bit data in this LSI. Unused pins (DB9-0) must be fixed to the Vcc or GND level. Ensure that upper bytes have to be written when writing the index register.
CSn* A1 H8/2245 HWR* (RD*) D15-0 8 10 GND
CSn* RS WR* (RD*) DB17-10 DB9-0
HD66776
Example of interface with 8-bit microcomputer Data format for 8-bit interface (1)
Interface
Input pin DB DB 17 16
First transfer (upper)
Second transfer (lower)
DB DB DB 15 14 13
DB DB 12 11
DB 10
DB 17
DB DB 16 15
DB DB DB 14 13 12
DB DB 11 10
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code
RAM data write
First transfer (upper) Second transfer (lower)
Input pin
DB DB 17 16
DB 15
DB 14
DB DB 13 12
DB 11
DB 10
DB DB DB 17 16 15
DB DB 14 13
DB 12
DB DB 11 10
GRAM write data
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel 65,536 colors are available in 8-bit system interface.
Rev.1.11, Oct. 02.2003, page 92 of 175
HD66776
Data format for 8-bit interface (2) Instruction First transfer (Upper) Input pin DB DB 17 16 DB DB DB DB 15 14 13 12 DB DB 11 10 Second transfer (Lower) DB DB DB DB 17 16 15 14 DB DB DB DB 13 12 11 10
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code RAM data write First transfer Input pin Second transfer Third transfer
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 11 10 17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10
GRAM write data
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
Data format for 8-bit interface (3) Instruction First transfer (Upper) Input pin DB DB 17 16 DB DB DB DB 15 14 13 12 DB DB 11 10 Second transfer (Lower) DB DB DB DB DB DB 17 16 15 14 13 12 DB DB 11 10
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Instruction code RAM data write First transfer Input pin DB DB DB DB DB DB 17 16 15 14 13 12 Second transfer DB DB DB DB DB DB 17 16 15 14 13 12 Third transfer DB DB DB DB DB DB 17 16 15 14 13 12
GRAM write data
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
Rev.1.11, Oct. 02.2003, page 93 of 175
HD66776 Note: Transfer synchronization function for an 8-bit bus interface The HD66776 supports the transfer synchronization function, which resets the upper/lower counter to count upper/lower 8-bit data transfer in the 8-bit bus interface. Noise causing transfer mismatch between the eight upper and lower bits can be corrected by a reset triggered by consecutively writing a 00H instruction four times. The next transfer starts from the upper eight bits. Executing synchronization function periodically can recover any runaway in the display system.
RS RD WR Upper/ DB17-10 Lower "00" H (1) "00"H (2) "00"H (3) "00"H (4) Upper Lower
(8-bit transfer synchronization)
Rev.1.11, Oct. 02.2003, page 94 of 175
HD66776 Serial clock synchronized interface (SPI) Setting the IM3 pin to the GND level, the IM2 pin to the Vcc level, the IM1 pin to the GND level allows standard clock-synchronized serial data (SPI) transfer, using the chip select line (CS*), serial transfer clock line (SCL), serial input data (SDI), and serial output data (SDO). For a serial interface, the IM0/ID pin function uses an ID pin. If the chip is set up for serial interface, the DB15-2 pins which are not used must be fixed at Vcc or GND. The HD66776 initiates serial data transfer by transferring the start byte at the falling edge of CS* input. It ends serial data transfer at the rising edge of CS* input. The HD66776 is selected when the 6-bit chip address in the start byte transferred from the transmitting device matches the 6-bit device identification code assigned to the HD66776. The HD66776, when selected, receives the subsequent data string. The least significant bit of the identification code can be determined by the ID pin. The five upper bits must be 01110. Two different chip addresses must be assigned to a single HD66776 because the seventh bit of the start byte is used as a register select bit (RS): that is, when RS = 0, data can be written to the index register can be read, and when RS = 1, an instruction can be issued or data can be written to or read from RAM. Read or write is selected according to the eighth bit of the start byte (R/W bit). The data is received when the R/W bit is 0, and is transmitted when the R/W bit is 1. When writing to RAM via this serial interface, the data is written to the GRAM after two-byte data has been transferred. The MSB of RB data is added to its LSB so that data to be written to the RAM will be 18 bits. After receiving the start byte, the HD66776 receives or transmits the subsequent data byte-by-byte. The data is transferred with the MSB first. All HD66776 instructions are 16 bits. Two bytes are received with the MSB first (DB15 to 0), then the instructions are internally executed. Data for RAM write is expanded to 18-bit data in this LSI.) After the start byte has been received, the first byte is fetched internally as the upper eight bits of the instruction and the second byte is fetched internally as the lower eight bits of the instruction. Four bytes of RAM read data after the start byte are invalid. The HD66776 starts to read correct RAM data from the fifth byte. Start Byte Format
Transfer Bit Start byte format S Transfer start 1 0 Note: ID bit is selected by the IM0/ID pin. 2 1 3 1 4 1 5 0 6 ID 7 RS 8 R/W
Device ID code
Rev.1.11, Oct. 02.2003, page 95 of 175
HD66776 RS and R/W Bis Function
RS 0 0 1 1 R/W 0 1 0 1 Function Sets index register Reads status Writes instruction or RAM data Reads instruction or RAM data
Data format for serial interface
Instruction
First transfer (Upper) Input pin D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 Second transfer (Lower) D5 D4 D3 D2 D1 D0
Instruction
IB 15
IB 14
IB 13
IB 12
IB 11
IB 10
IB 9
IB 8
IB 7
IB 6
IB 5
IB 4
IB 3
IB 2
IB 1
IB 0
Inst ucti n code ro
RAM data write
First transfer (Upper) Input pin D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 Second transfer (Lower) D5 D4 D3 D2 D1 D0
GRAM R5 write data
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pixel
65,536 colors are available in SPI.
Rev.1.11, Oct. 02.2003, page 96 of 175
HD66776 Procedure for Transfer on Clock-Synchronized Serial Bus Interface
a)Timing if Basic Data-transfer through Clock-Synchronized Serial Bus Interface
Transfer start Transfer end
CS* (Input)
SCL (Input) SDI (Input)
1
2
3
4
5
6
7
8
9 10
11 12
13 14 15 16
17 18 19 20 21 22 23
24
MSB
"0" "1" "1" "1" "0" Device ID code
ID RS RS RW RW D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1
LSB
D0
Start byte
SDO (Output)
Index register setting, instruction, RAM data write
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Instruction read, RAM data read
b) Timing of consecutive Data-Transfer through Clock-Synchronized Serial Bus Interface
CS* (Input)
1 234 5 67 8 9 10 1112 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SCL (Input)
SDI (Input)
Start byte Start
Instruction1: upper eight bits
Instruction1: lower eight bits
Instruction2: upper eight bits Instruction1: execution time End
Rev.1.11, Oct. 02.2003, page 97 of 175
HD66776 Procedure for Transfer on Clock-Synchronized Serial Bus Interface (cont)
c) RAM Data/Instruction Read
CS* (Input) SCL (Input) SDI (Input) SDO (Output) Start Note: Fifth bytes of the RAM read data after the start byte are invalid. The HD66776 starts to read the correct RAM data from the sixth byte.
Start byte RS = 1, R/W = 1 RAM Read: Upper eight bits RAM Read: lower eight bits
Dummy Read 1
Dummy Read 2
Dummy Read 3
Dummy Read 4
Dummy Read 5
End
d) Status Read/Instruction Read
CS* (Input) SCL (Input) SDI (Input) SDO (Output) Start Note: One byte of the read data after the start byte are invalid. The HD66776 starts to read the correct data from the second byte.
Start byte RS = 1, R/W = 1
Dummy read 1
Upper eight bits
Lower eight bits End
Rev.1.11, Oct. 02.2003, page 98 of 175
HD66776 VSYNC Interface The HD66776 incorporates VSYNC-I/F, which enables moving pictures to be displayed with only the system interface and the frame synchronization signal (VSYNC). This interface requires minimal changes from the system interface to display moving pictures.
VSYNC LCDC/MPU CS* RS WR * DB17-0, 8 -1 16
When DM1-0 = "10" and RM = "0", VSYNC-I/F is available. In this interface the internal display operation is synchronized with VSYNC. Data for display is written to RAM via the system interface with higher speed than for internal display operation. This method enables flicker-free display of moving pictures with the system interface. Display operation can be achieved by using the internal clock generated by the internal oscillator and the VSYNC input. Because all the data for display is written to RAM, only the data to be rewritten is transferred. This method reduces the amount of data transferred during moving picture display operation. The high-speed write mode (HWM1-0 = "11") achieves both low power consumption and high-speed access.
VSYNC
Updating of screen
RAM write via system interface Display operation in synchronization with the internal clock
Updating of screen
Note:Data for display should be written in the high-speed write mode (HWM1-0 ="11") when VSYNC-I/F is in use.
Rev.1.11, Oct. 02.2003, page 99 of 175
HD66776 VSYNC-I/F requires taking the minimum speed for RAM writing via the system interface and the frequency of the internal clock into consideration. RAM writing should be performed with higher speed than the result obtained from the calculation shown below.
* * Internal clock frequency (fosc) [Hz] = Frame frequency x (Display raster-row (NL) + Front porch (FP) + Back porch (BP)) x 16 Clock x Fluctuation Minimum speed for RAM writing [Hz] > 256 x Display raster-row (NL) / {((Back porch (BP) + Display rasterrow (NL) - Margin) x 16 clock) / fosc}
Note: When RAM writing does not start immediately after the falling edge of VSYNC, the time between the falling edge of VSYNC and the RAM writing start timing must also be considered. An example is shown below. Example Display size 256 RGB x 320 raster-rows Display raster-row 320 raster-rows (NL = 100111) Back/front porch 14/2 raster-rows (BP = 1110/FP = 0010) Frame frequency 60 Hz Internal clock frequency (fosc) Hz = 60 Hz x (320 + 2 + 14) x 16 Clock x 1.1 / 0.9 = 394 kHz Note 1: Calculating the internal clock frequency requires considering the fluctuation. In the above case a 10% fluctuation within the VSYNC period is assumed. Note 2: The fluctuation includes LSI production variation and air temperature fluctuation. Other fluctuations, including those for the external resistors and the supplied power, are not included in this example. Please keep in mind that a margin for these factors is also needed. Minimum speed for RAM writing Hz > 256 x 320 / {((14 + 320 - 2) raster-rows x 16 clock) / 394 kHz} = 6.08 MHz Note 3: In this case RAM writing starts immediately after the falling edge of VSYNC. Note 4: The margin for display raster-row should be two raster-rows or more at the completion of RAM writing for one frame.
VSYNC Back porch line 14 lines
Raster-rows to be operated
RAM Writing
Raster-row 320
RAM write at 10MHz 81920 times
R-C oscillation 10% Display operation
RAM write at 6.08 MHz
Display 320 raster-rows
Display operation
Display operation
Front porch (2 raster-r ws) o Brank period
0 Back-porch 14H VSYNC
[ms] 8.19 13.47 13.56 16.67
Operation for VSYNC Interface
Rev.1.11, Oct. 02.2003, page 100 of 175
HD66776 Usage on VSYNC Interface 1. The Example above is a calculated value. Please keep in mind that a margin for these factors is also needed. Because production variation of the internal oscillator requires consideration. 2. The example above is a calculated value of rewriting the whole screen. A limitation of the moving picture area generates a margin for the RAM write speed.
Example: Moving image display area (20 to 300 raster-row))
Raster-row 320 300 R-C oscillation 10% Display operation
RAM Write Back porch (14 raster-rows) (20 raster-rows)
Raster-rows to be operated
RAM write at 6.08 MHz Display operation
Moving picture area (280 raster-rows)
20 (20 raster-rows) Front porch (2 raster-rows) VSYNC 0 Back-porch 14H 4.22 11.79 13.56 [ms] 16.57
Limitation of Moving Picture Area
3. During the period between the completion of displaying one frame data and the next VSYNC signal, the display will remain front porch period. 4. Transition between the internal clock operation mode (DM1-0 = 00) and VSYNC interface mode will be valid after the completion of the screen which is displayed when the instruction is set. 5. Partial display, vertical scroll, and interlaced driving functions are not available on VSYNC interface mode. 6. The VSYNC interface is performed by the method above, therefore, AM bit should be 0. 7. Data for display should be written in high-speed write mode (HWM1-0 = 11) when the VSYNC interface is in use.
Rev.1.11, Oct. 02.2003, page 101 of 175
HD66776
Internal clock operation
RGB I/F operation
Display operation in synchronization with the RGB signal The value set in DM1-0 and RM will be valid after completion of 1-frame display.
HWM = 1-0 = 11, AM = 0 Address Setting RGB I/F Setting
(DM1-0 = 01, RM =1)
Display operation in synchronization with the internal clock The value set in DM1-0 and RM will be valid after completion of 1-frame display.
Internal clock mode setting (DM1-0 = 00, RM=0)
Wait more than 1 frame Internal clock operation
Display operation in synchronization with the internal clock
Index resister setting
(202h)
Wait more than 1 frame RGB I/F Writing RAM Data
Note: When switching to RGB I/F, please input RGB I/F signals (VSYNC, HSYNC, DOTCLK, ENABLE) before DM1-0, RM setting.
Display operation in synchronization with the RGB signal
Wait more than 1 frame
Note: When the interface mode is switched, VSYNC, HSYNC, DOTCLK, and ENABLE should be input before setting of DM1-0 and RM.
Transition between the Internal Operating Clock Mode and RGB Interface Mode
Rev.1.11, Oct. 02.2003, page 102 of 175
ot
ot
Internal clock operation
RGB I/F (1)
RGB I/F (1)
Internal clock operation
HD66776
External Display Interface
The following interfaces are available as external display interface. It is determined by setting bits of RIM1-0. RAM accesses can be performed via the RGB interface. RIM Bits
RIM1 0 0 1 1 RIM0 0 1 0 1 RGB Interface PD Pin
18-bit RGB interface 16-bit RGB interface 6-bit RGB interface Setting disabled
PD17-0 PD17-13, 11-1 PD17-12
Note: Multiple interfaces cannot be used. RGB interface The RGB-I/F is performed in synchronization with VSYNC, HSYNC, and DOTCLK. Combining the function of the high-speed write mode (HWM1-0 = 11) and the window address enables transfer only the screen to be updated and reduce the power consumption.
VSYNC
Back porch period (BP3-0)
Display area for RAM data
Display area for moving pictures
Display period (NL5-0)
Front porch period (FP3-0)
HSYNC
DOTCLK
Note: Until the next VSYNC signal is input, the dislay will remain back porch period
ENABLE VLD
PD17-0
VSYNC:Frame synchronization signal HSYNC:Raster-row synchronization signal DOTCLK:Dot clock ENABLE:Data enable signal VLD: Data valid signal PD17-0: Display data for RGB (6:6:6)
Back porch period (BPP):14H>=BP3-0>=2H Front porch period (FPP):14H>FP3-0>=2H FPP + BPP = 16H Display operation period:NL5-0=<320H The number of raster-rows of 1 frame: FPP + DP + BPP
Rev.1.11, Oct. 02.2003, page 103 of 175
HD66776 VLD and ENABLE signals The relationship between VLD and ENABLE signals is shown below. Relationship between VLD and ENABLE
ENABLE 0 0 1 VLD 0 1 * RAM Write Valid Invalid Invalid RAM Address Updated Updated Hold
Rev.1.11, Oct. 02.2003, page 104 of 175
HD66776 RGB interface timing 16/18-bit RGB interface timing Timing chart for RGB-I/F is shown below.
1 frame Back porch period VSYNC HSYNC DOTCLK ENABLE VLD PD17-0 Front porch period
>= 1H VSYNC 1H HLW>=1CLK HSYNC 1 CLK DOTCLK DTST >= HLW ENABLE VLD
PD17-0 Valid data
VLW: The period in which VSYNC is low level HLW: The period in which HSYNC is low level DTST: Set up time for data transfer
Note: Data for display should be written in the high-speed write mode (HWM1-0=11) in RGB-I/F is in use.
Rev.1.11, Oct. 02.2003, page 105 of 175
HD66776 6-bit RGB interface timing Timing chart for RGB-I/F is shown below.
1 frame Back porch period VSYNC HSYNC DOTCLK ENABLE VLD PD17-12 Front porch period
>= 1H VSYNC 1H HLW>=3CLK HSYNC 1 CLK DOTCLK DTST >= HLW ENABLE VLD
RGB RGB RGB RGB RGB
PD17-12 Valid data
VLW: The period in which VSYNC is low level HLW: The period in which HSYNC is low level DTST: Set up time for data transfer Note 1:These clocks are regarded as one pixel for transfer when data is transferred in 6-bit interface. 2: VSYNC,. HSYNC., EVABLE, DOTCLK, VLC, and PD17-2 should be transferred in units of three clocks. 3: Data for display should be written in the high-speed write mode (HWM1-0=11) in RGB-I/F is in use.
Rev.1.11, Oct. 02.2003, page 106 of 175
HD66776 Moving picture display The HD66776 incorporates RGB interface to display moving pictures and RAM to store data for display. For displaying moving pictures, the HD66772 has the following features. Moving picture area can only be transferred by the window address function The high-speed write mode achieves both low power consumption and high-speed access Moving picture area to be rewritten can only be transferred. Reducing the amount of data transferred enables reduce the power consumption to the whole system. Still picture area, such as an icon, can be updated while displaying moving pictures combining with the system interface. RAM access via the system interface when RGB-I/F is in use RAM can be accessed via the system interface when RGB-I/F is in use. When data is written to RAM during RGB-I/F mode, the ENABLE bit should be high to stop data writing via RGB-I/F, because RAM writing is always performed in synchronization with the DOTCLK input when ENABLE is low. When RM = "0", RAM access via the system interface is available. Before the next RAM access via RGB-I/F, set RM = "1" and index to R202h after waiting some time for a write/read bus cycle. When a RAM write conflict occurs, data writing is not guaranteed. Example of display moving picture via RGB-I/F and updating still picture via the system interface are shown below.
Rev.1.11, Oct. 02.2003, page 107 of 175
HD66776
Updating Updating
VSYNC ENABLE DOTCLK PD17-0
Setting of index System interface Index R202 Updating or moving picture area RM=0 Setting Index of R202 address Updating of area other than moving picture area RM=1 Setting of address Index R202 Updating or moving picture area
U p d a ti n g o f s t i l l p i c t u r e area*1
Note 1: When RGB-I/F is in use, an address is set at every falling edge of VSYNC. 2: An address and an index (R202h) should be set before RAM is accessed via RGB-I/F. 3: The high-speed write mode (HWM1-0 = "11") should be used in RGB-I/F and VSYNC-I/F.
2001/01/01 00:00 Still picture area
Moving picture area
Example of Updating Still Picture Area during Diaplaying Moving Picture
Rev.1.11, Oct. 02.2003, page 108 of 175
HD66776 6-bit RGB interface 6-bit RGB interface can be used by setting RIM1-0 to 10. Display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Data for display is transferred to the internal RAM via 6-bit RGB data bus (PD17-12), the data valid signal (VLD), and the data enable signal (ENABLE). Unused pins (DB11 to 0) must be fixed to the Vcc or GND level. Note: Instructions should be set via the system interface.
VSYNC HSYNC DOTCLK LCDC VLD ENABLE DB17-12 6 12 GND HD66776
Data format for 6-bit interface First transfer INPUT PD 17 PD 16 PD 15 PD 14 PD 13 PD PD 12 17 Second transfer PD 16 PD 15 PD 14 PD PD 13 12 PD 17 PD 16 Third transfer PD 15 PD 14 PD 13 PD 12
Write Data R5 to GRAM
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One Pixel
262,144 colors are available in 6-bit system interface.
Rev.1.11, Oct. 02.2003, page 109 of 175
HD66776 Note: Transfer synchronization function for a 6-bit bus interface The HD66776 has the transfer counter to count 1st, 2nd and 3rd data transfer in the 6-bit bus interface. The transfer counter is reset on the falling edge of VSYNC and enters the 1st data transmission state. Transfer mismatch can be corrected by a reset triggered on the falling edge of VSYNC, which means the beginning of a frame. The next transfer restarts correctly. In this method, when data is consecutively transferred such as displaying moving pictures, the effect of transfer mismatch will be reduced and recover normal operation. Note: The internal display is operated in units of three DOTCLK. When the DOTCLK is not input in units of pixels, clock mismatch occurs and the frame which is operated and the next frame are not displayed correctly.
VSYNC
ENABLE DOTCLK PD17-0
2nd transfer 1st transfer 2nd 3rd transfer transfer 1st transfer 2nd transfer 3rd transfer
Transfer synchronization
Rev.1.11, Oct. 02.2003, page 110 of 175
HD66776 16-bit RGB interface 16-bit RGB interface can be used by setting RIM1-0 to "01". Display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Data for display is transferred to the internal RAM in synchronization with display operation via 16-bit RGB data bus (PD17-13 and 11-1), the data valid signal (VLD) and data enable signal (ENABLE). Note: Instructions should be set via the system interface.
VSYNC HSYNC DOTCLK LCDC VLD ENABLE 16 2 GND Data format for 16-bit interface HD66776
DB17-13, 11-1
Inp u t
PD PD PD PD PD 17 16 15 14 13
PD PD PD PD PD 11 10 9 8 7
PD PD PD PD PD PD 6 5 4 3 2 1
Write data to GRAM
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pi xel
Rev.1.11, Oct. 02.2003, page 111 of 175
HD66776 18-bit RGB interface 18-bit RGB interface can be used by setting RIM1-0 to "00". Display operation is synchronized with VSYNC, HSYNC, and DOTCLK signals. Data for display is transferred to the internal RAM in synchronization with display operation via 18-bit RGB data bus (PD17-0), the data valid signal (VLD) and data enable signal (ENABLE). Note: Instructions should be set via the system interface.
VSYNC HSYNC DOTCLK LCDC VLD ENABLE DB17-0 18 HD66776
Data format for 18-bit interface
t Inp u PD PD PD PD PD PD 17 16 15 14 13 12 PD 0
PD PD PD PD PD 11 10 9 8 7
PD PD PD PD PD PD 6 5 4 3 2 1
Write data to GRRAM
R5
R4
R3 R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
One pi xel 262,144 colors are available in 18 RGB I/ . -bit F
Rev.1.11, Oct. 02.2003, page 112 of 175
HD66776 Usage on external display interface a) When external display interface is in use, the following functions are not available. Relationship between VLD and ENABLE
Function Partial display Scroll function Graphics operation function External Display Interface Not available Not available Not available Internal Display Operation Available Available Available
b) VSYNC, HSYNC, and DOTCLK signals should be supplied during display operation via RGB-I/F. c) RGB data is transferred for three clock cycles in 6-bit RGB-I/F. Data transferred, therefore, should be transferred in units of RGB. d) Interface signals, VSYNC, HSYNC, DOTCL, ENABLE, VLD,6-bit RGB-I/F and PD17-12 should be set in units of RGB (pixels) to match RGB transfer. e) Transitions between internal operation mode and external display interface should follow the mode transition sequence shown below. f) During the period between the completion of displaying one frame data and the next VSYNC signal, the display will remain front porch period. g) RGB-I/F should be used in high-speed write mode (HWM1-0 = 11). h) An address set is done on the falling edge of VSYNC every frame in RGB-I/F.
ot ot
Internal clock operation RGB I/F (1) RGB I/F (1) Internal clock operation
Internal clock operation
RGB I/F operation
Display operation in synchronization with the RGB signal The value set in DM1-0 and RM will be valid after completion of 1-frame display.
HWM = 1-0 = 11, AM = 0 Address Setting RGB I/F Setting
(DM1-0 = 01, RM =1)
Display operation in synchronization with the internal clock The value set in DM1-0 and RM will be valid after completion of 1-frame display.
Internal clock mode setting (DM1-0 = 00, RM=0)
Wait more than 1 frame Internal clock operation
Display operation in synchronization with the internal clock
Index resister setting
(202h)
Wait more than 1 frame RGB I/F Writing RAM Data
Note: When switching to RGB I/F, please input RGB I/F signals (VSYNC, HSYNC, DOTCLK, ENABLE) before DM1-0, RM setting.
Display operation in synchronization with the RGB signal
Wait more than 1 frame
Note: When the interface mode is switched, VSYNC, HSYNC, DOTCLK, and ENABLE should be input before setting of DM1-0 and RM.
Transition between the Internal Operating Clock Mode and RGB Interface Mode
Rev.1.11, Oct. 02.2003, page 113 of 175
HD66776 Writing RAM data from system I/F during displaying RGB I/F
From RGB I/F (1) to RGB I/F (2) RGB I/F Operation
From RGB I/F (2) to RGB I/F (1)
RGB I/F mode setting (DM1-0=01, RM=0) HWM1-0 =11/00 Address Setting Index resister setting (R202h)
System I/F Writing RAM Data
HWM1-0 =11, AM=0 Address Setting RGB I/F mode (DM1-0=01, RM=1) Index resister setting (R202h)
System I/F Writing RAM Data
RGB I/F Operation
Rev.1.11, Oct. 02.2003, page 114 of 175
HD66776
High-Speed Burst RAM Write Function
The HD66776 has a high-speed burst RAM-write function that can be used to write data to RAM in onefourth the access time required for an equivalent standard RAM-write operation. This function is especially suitable for applications which require the high-speed rewriting of the display data, for example, display of color animations, etc. When the high-speed RAM-write mode (HWM) is selected, data for writing to RAM is once stored to the HD66776 internal register. When data is selected four times per word, all data is written to the on-chip RAM. While this is taking place, the next data can be written to an internal register so that high-speed and consecutive RAM writing can be executed for animated displays, etc.
a) Action flow of high-speed consecutive RAM writing
Microcomputer
18
Address counter (AC) 17 00000" " H 00001" " H GRAM Register 1 Register 2 18 n x Register n
0000n" " H
b) Wxample of high-speed consecutive RAM writing
CS* (input) 1 WR (input) DB17 -0 (input/output) Index Index RAM RAM data data (R202) (R22) 1 2
RAM RAM RAM data data data n n+ n + 1 2 RAM write execution time RAM RAM RAM data data data 2n 2n+ 2n+ 1 3 RAM write execution time RAM data (n+) to (2n) 1
2
n
1
2
n
1
2
n
RAM data 3n
Index
Data
RAM write ote execution time * N RAM data (2n+) to (3) 1 n
RAM write data (18 n bit) x RAM address (AC16 t (AC15o 0)
RAM data 1 to n
" 000" -" 000n" 0 H0 H
" 0100" -"0 0 H 010n" H
" 0200" -"0 0 H 020n" H
Note: When a high-speed RAM wirte is canceled, the next instruction must only be executed after the RAM write execution time has elapsed (Bus cycle fire (tCYC) at normal write mode).
Rev.1.11, Oct. 02.2003, page 115 of 175
HD66776 When high-speed RAM write mode is used, note the following. Notes: 1. RAM writing is executed by one-raster-row. And data is not written into RAM when writing is finished before data fills the horizontal window setting area. 2. When the index register and RAM data write (202H) have been selected, the data is always written first. RAM cannot be written to and read from at the same time. HWM1-0 must be set to "00" while RAM is being read. 3. High-speed and normal RAM write operations cannot be executed at the same time. The mode must be switched and the address must then be set. Comparison between Normal and High-Speed RAM Write Operations
Normal RAM Write 0= "00") BGR function Write mask function RAM address set RAM read RAM write Window address Can be used Can be used Can be specified by word unit Can be read by word unit Can be written by word unit Can be set by word unit (Minimum range: 1 word x 1 line) (HWM1High-Speed RAM Write (HWM1-0= "11") Can be used Can be used Can be specified by word unit Can not be used Can be written by every rasterrow More than eight words are needs to be set. Can be set by word unit. (Minimum range: 8 word x 1 line) External display interface Can be used Can be used
Rev.1.11, Oct. 02.2003, page 116 of 175
HD66776 High-Speed RAM Write in the Window Address When a window address range is specified, RAM data which is in an optional window area can be rewritten consecutively and quickly. An example of high-speed RAM write with a window address-range specified is shown below. The window address-range can be rewritten to consecutively and quickly by using the window addressrange specification bits (HSA7 to 0, HEA7 to 0).
h00000
Writing in the horizontal direction AM = ID0 = "0", "1" Window address-range setting HAS = h12, HEA = h30 VSA = h80,VEA = hA0 High-speed RAM write mode setting HWM1-0 = "11"
GRAM address map h00812
Window address-range specification (rewrite area)
Address set AD = h00810 *Note
h0A030 h13FF F
RAM write X 31 X152
Window address-range setting HA S = h1 2, HE A = h 30 VS A = h8 0, VEA = hA 0
Note: Set within the Window area.
Example of the High-Speed RAM Write with a Window Address-Range Specification
Rev.1.11, Oct. 02.2003, page 117 of 175
HD66776
Window Address Function
When data is written to the on-chip GRAM, a window address-range which is specified by the horizontal address register (start: HSA7 to 0, end: HEA 7 to 0) or the vertical address register (start: VSA8 to 0, end: VEA8 to 0) can be written to consecutively. Data is written to addresses in the direction specified by the AM bit (increment/decrement). When image data, etc. is being written, data can be written consecutively without thinking a data wrap by doing this. The window must be specified to be within the GRAM address area described below. Addresses must be set within the window address. [Restriction on window address-range settings] (Horizontal direction) 00H HEA7 to 0 HEA7 to 0 "FF"H (Vertical direction) 00H VSA8 to 0 VEA8 to 0 "13F"H [Restriction on address settings during the window address] (RAM address) HSA7 to 0 AD7 to 0 HEA7 to 0 VSA8 to 0 AD16 to 8 VEA8 to 0
GRAM address map
"00000"H "000FF"H
Window address area
"02010"H "02110"H "0202F"H "0212F"H
"05F10"H
"05F2F"H
"13F00"H
"13FFF"H
Window address-range specification area HSA7 to 0 = "10"H, HEA 7 to 0 = "2F"H VSA8 to 0 = "020"H, VEA8 to 0 = "05F"H
I/D = "1" (increment) AM = "0" (horizontal writing)
Example of Address Operation in the Window Address Specification
Rev.1.11, Oct. 02.2003, page 118 of 175
HD66776
Graphics Operation Function
The HD66776 can greatly reduce the load of the microcomputer graphics software processing through the 18-bit bus architecture and internal graphics-bit operation function. This function supports the following: 1. A write data mask function that selectively rewrites some of the bits in the 18-bit write data. The graphics bit operation can be controlled by combining the entry mode register, the bit set value of the RAM-write-data mask register, and the write from the microcomputer. Graphics Operation
Operation Mode Write mode 1 Write mode 2 I/D 0/1 0/1 AM 0 1 Operation and Usage Horizontal data replacement Vertical data replacement
Microcomputer 18
+1/-1
+25 6
Wirte-data latch 18
Address counter (AC) 18 Write bit mask Write-mask register (WM17-0)
17
Graphics RAM (GRAM)
Data Processing Flow of the Graphics Operation
Rev.1.11, Oct. 02.2003, page 119 of 175
HD66776 Write-data Mask Function The HD66776 expands 16-bit data sent from the microcomputer to 18-bit data (when 18-bit interface is in use, data is not expanded). A bit-wise write-data mask function controls writing the 18-bit data from the microcomputer to the GRAM. Bits that are 0 in the write-data mask register (WM17-0) cause the corresponding DB bit to be written to the GRAM. Bits that are 1 prevent writing to the corresponding GRAM bit to the GRAM; the data in the GRAM is retained. This function can be used when only onepixel data is rewritten or the particular display color is selectively rewritten.
DB0
DB17
Data written by the microcomputer
R05 R04 R03 R02 R01 R00 G05 G04 G03 G02 G02 G01 G00 B05 B04 B03 B02 B01 B00
WM17
WM0
Write-data mask
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
17
0
GRAM data
*
*
*
*
*
*
G05 G04 G03 G02 G02 G01 G00
*
*
*
*
B01 B00
Note: Data is expanded to 18 bits when 8-/16-bit system and 16-bit RGB interfaces.
Rev.1.11, Oct. 02.2003, page 120 of 175
HD66776 Graphics Operation Processing 1. Write mode 1: AM = "0" This mode is used when the data is horizontally written at high speed. It can also be used to initialize the graphics RAM (GRAM) or to draw borders. The write-data mask function (WM17-0) are also enabled in these operations. After writing, the address counter (AC) automatically increments by 1 (I/D = "1") or decrements by -1 (I/D = "0"), and automatically jumps to the counter edge one-raster-row below after it has reached the left or right edge of the GRAM.
Operation example 1) I/D - "1",AM = "0" 2) WM17-0 = "007FF"H 3) AC = "00000"H
WM17 Write-data mask: WM0 *Write mask for pl in G and B. a
000000111111111111
DB17 DB0
Write-data ( ) 1 Write-data ( ) 2
100111111100101000 110001000001100000
00000" " H
Data is expanded to 18 bits when 8-/16-bit system and 16-bit RGB interfaces.
00001" " H
100111 * * * * * * * * * * * * 110001 * * * * * * * * * * * *
Write-data ( ) 1 Write-data ( ) 2
" 0 00 2 " 0 H
GRAM
Note: he bits in the GRAM indicated T by " "are not changd. * e
2. Write mode 2: AM = "1" This mode is used when the data is vertically written at high speed. It can also be used to initialize the GRAM, develop the font pattern in the vertical direction, or draw borders. The write-data mask function (WM17-0) are also enabled in these operations. After writing, the address counter (AC) automatically increments by 256, and automatically jumps to the upper-right edge (I/D = "1") or upperleft edge (I/D = "0") following the I/D bit after it has reached the lower edge of the GRAM.
Operation example 1) I/D = "1", AM = "1" 2) WM17-0 = "007FF"H 3) AC = "00000"H
WM17 Write-data mask: WM0
000000111111111111
DB17 DB0 Data is expanded to 18 bits when 8-/16-bit system and 16-bit RGB interfaces.
Write-data (1) : Write-data (2) : Write-data (3) :
100111111100101000 110001000001100000 011110100010000011 100111 * * * * * * * * * * * * 110001 * * * * * * * * * * * * 011110 * * * * * * * * * * * *
"00000"H "00100"H "00200"H
Write-data (1) Write-data (2) Write-data (3)
GRAM
Note1: The bits in the GRAM indicated by "*" are not changed. Note2: After writing to 13F00H, the address counter value becomes 00001H.
Rev.1.11, Oct. 02.2003, page 121 of 175
HD66776
-Correction Function
The HD66776 incorporates a -correction function to simultaneously display 262,144 colors. The correction operation specifies eight levels of grayscale with gradient-adjustment and fine-adjustment registers. Select the polarity of these registers to match the LCD panel used. These registers are available for both polarities.
MS B
Displ y Data a
Graphics RAM (GRA M)
LS B B5 B4 B3 B2 B1 B0
R5 R4 R3 R2 R1 R0
G5 G4 G3 G2 G1 G0
P P02 P P01 P P00 PK PK PK P P12 P P11 P P10 PK PK PK P P22 P P21 P P20 PK PK PK P P32 P P31 P P30 PK PK PK
Register of positive polarity
P P42 P P41 P P40 PK PK PK P PK
52
V0 V1
Grayscal amplifier e
P PK
51
P PK
50
6
6
6
PRP02 PRP01 PRP00 PRP12 PRP11 PRP10 VRP 03 VRP 02 VRP 01 VRP 00 VRP 14 VRP 13 VRP 12 VRP 11 VRP 10
8
64
64grayscale control
64grayscale control
64grayscale control
V63
LCD Driver
LCD Driver
LCD Driver
PKN 02 PKN 01 PKN 00 PKN 12 PKN 11 PKN 10 PKN 22 PKN 21 PKN 20
Register of negative polarity
PKN 32 PKN 31 PKN 30 PKN 42 PKN 41 PKN 40 PKN 52 PKN 51 PKN 50 PRN02 PRN01 PRN00 PRN12 PRN11 PRN10 VRN 03 VRN02 VRN01 VRN00
R
G
LCD
B
VRN 14 VRN 13 VRN 12 VRN 11 VRN 10
Rev.1.11, Oct. 02.2003, page 122 of 175
HD66776 Configuration of Grayscale Amplifier Eight levels (VIN0-7) are specified by the gradient-adjustment and fine-adjsutment registers. 64-levels (V0-63) are generated by ladder resistors, which divide each level specified by the registers into more detailed levels.
Register for gradi ent adjustment
Registers for fine adjustment (6 x 3 bits)
Register for ampltude i adj stment u
PRP/N0 PRP/N1 PKP/N0 PKP/N1 PKP/N2 PKP/N3 PKP/N4 PKP/N5 VRP/N0 VRP/N1
VDH
3
3
3
3
3
3
3
3
4
5
VINP0/VINN0
V0
VINP1/VINN1
8 to 1 selector
V1 V2 V3
VINP2/VINN2
8 to 1 selector
V8 V9
Gray scale amplifier i
Ladder resistor
VGS
8 to 1 selector
VINP3/VINN3
V20 V21
8 to 1 selector
V43 V44 V55 V56 V57
VINP4/VINN4
8 to 1 selector
VINP5/VINN5
VINP6/VINN6
8 to 1 selector
V62
VINP7/VINN7
V63
Rev.1.11, Oct. 02.2003, page 123 of 175
HD66776
VDH
VRP0 0 15R 5R RP0 RP1 RP2 RP3 RP4 RP5 RP6 RP7 KVP1 KVP2 KVP3 KVP4 KVP5 KVP6 KVP7 KVP8 PRP0[2:0] RP8 RP9 RP10 RP11 RP12 RP13 RP14 5R RP15 PR16 PR17 PR18 PR19 PR20 PR21 PR22 RP23 PR24 PR25 PR26 PR27 PR28 PR29 PR30 RP31 PR32 PR33 PR34 PR35 PR36 PR37 PR38 KVP33 KVP34 KVP35 KVP36 KVP37 KVP38 KVP39 KVP40 PRP1[2:0] PR39 PR40 PR41 PR42 PR43 PR44 PR45 RP46 KVP49 VINP7 VRP1 0-31R 8R RP47 PRP1[4:0] VRN1 0-31R 8R RN47 PRN1[4:0] KVP41 8 to 1 KVP42 selector KVP43 KVP44 KVP45 KVP46 KVP47 KVP48 8 to 1 selector VINP5 1R KVP25 KVP26 KVP27 KVP28 KVP29 KVP30 KVP31 KVP32 8 to 1 selector VINP4 1R KVP17 KVP18 KVP19 KVP20 KVP21 KVP22 KVP23 KVP24 8 to 1 selector VINP3 1R KVP9 8 to 1 KVP10 selector KVP11 KVP12 KVP13 KVP15 KVP14 KVP16 8 to 1 selector VINP1 4R PRP0[3:0] KVP0 VINP0 PKP0[2:0] 5R RN0 RN1 RN2 RN3 RN4 RN5 RN6 RN7 KVN1 KVN2 KVN3 KVN4 KVN5 KVN6 KVN7 KVN8 PRN0[2:0] RN8 RN9 RN10 RN11 RN12 RN13 RN14 5R RN15 RN16 RN17 RN18 RN19 RN20 RN21 RN22 RN23 RN24 RN25 RN26 RN27 RN28 RN29 RN30 RN31 RN32 RN33 RN34 RN35 RN36 RN37 RN38 KVN33 KVN34 KVN35 KVN36 KVN37 KVN38 KVN39 KVN40 PRN1[2:0] RN39 RN40 RN41 RN42 RN43 RN44 RN45 RN46 KVN49 VINN7 KVN41 KVN42 KVN43 KVN44 KVN45 KVN46 KVN47 KVN48 8 to 1 selector VINN6 8 to 1 selector VINN5 KVN25 KVN26 KVN27 KVN28 KVN29 KVN30 KVN31 KVN32 8 to 1 selector VINN4 KVN17 KVN18 KVN19 KVN20 KVN21 KVN22 KVN23 KVN24 8 to 1 selector VINN3 KVN9 KVN10 KVN11 KVN12 KVN13 KVN14 KVN15 KVN16 8 to 1 selector VINN2 8 to 1 selector VINN1 PKN0[2:0] VRN0 0 15R PRP0[3:0]
4R
VRHP 0-28R
PKP1[2:0]
VRHN 0-28R
PKN12:0]
1R
VINP2
1R
PKP2[2:0]
PKN2[2:0]
1R
16R
PKP3[2:0]
16R
PKN3[2:0]
1R
5R
PKP4[2:0]
5R
PKN4[2:0]
1R
VRLP 0-28R
PKP5[2:0]
VRLN 0-28R
PKN5[2:0]
4R
VINP6
4R
5R
5R
EXVR
Ladder Amplifiers and 8 to 1 Selectors
Rev.1.11, Oct. 02.2003, page 124 of 175
HD66776 -Correction Registers This block has register groups for specifying a grayscale voltage that meets the -characteristics for the LCD panel used. These registers are divided into three groups, which correspond to the gradient, amplitude, and fine adjustment of the grayscale characteristics for the voltage. The polarity of each register can be specified independently (R, G, and B are common.).
Grayscale voltage
Grayscale voltage
Grayscale number Gradient adjustment
Grayscale number Amplitude adjustment
Grayscale voltage
Grayscale number Fine adjustment
1. Gradient adjustment registers The gradient adjustment registers are used to adjust the gradient in the middle of the grascale characteristics for the voltage without changing the dynamic range. This function is implemented by controlling the variable resistor (VRHP (N)0/VRL(N)1) in the ladder resistor block for grayscale voltage generation. A register can be separated into positive/negative polarities to perform an asymmetric drive. 2. Amplitude adjustment registers The amplitude adjustment registers are used to adjust the amplitude of the grayscale voltage. This function is implemented by controlling the variable resistor (VRP (N)/0VRP(N)1) under the ladder resistor block for grayscale voltage generation. The VDH level can be adjusted higher. There is an independent register on the positive/negative polarities as well as the gradient adjustment register. 3 Fine adjustment registers The fine adjustment register is no make subtle adjustment of the grayscale voltage level. To accomplish the adjustment, it controls the each reference voltage level by the 8 to 1 selector towards the 8-leveled reference voltage generated from the ladder resistor. Also, there is an independent register on the positive/negative polarities as well as other adjustment registers.
Rev.1.11, Oct. 02.2003, page 125 of 175
HD66776 Correction Registers
Register Groups Gradient adjustment Amplitude adjustment Fine adjustment Positive Polarity PRP0 2 to 0 PRP1 2 to 0 VRP0 3 to 0 VRP1 4 to 0 PKP0 2 to 0 PKP1 2 to 0 PKP2 2 to 0 PKP3 2 to 0 PKP4 2 to 0 PKP5 2 to 0 Negative Polarity PRN0 2 to 0 PRN1 2 to 0 VRN0 3 to 0 VRN1 4 to 0 PKN0 2 to 0 PKN1 2 to 0 PKN2 2 to 0 PKN3 2 to 0 PKN4 2 to 0 PKN5 2 to 0 Description Variable resistor VRHP (N) Variable resistor VRLP (N) Variable resistor VRP (N)0 Variable resistor VRP (N) 1 8-to-1 selector (voltage level of grayscale 1) 8-to-1 selector (voltage level of grayscale 8) 8-to-1 selector (voltage level of grayscale 20) 8-to-1 selector (voltage level of grayscale 43) 8-to-1 selector (voltage level of grayscale 55) 8-to-1 selector (voltage level of grayscale 62)
Ladder resistors and 8 to 1 selector Block configuration The block consists of two ladder resistors including variable one, and 8 to 1 selector which selects one voltage level generated by the ladder resistors and outputs the reference voltage for grayscale voltage. Furthermore, the block has pins to connect a variable resistor. It can adjust the variation between panels. Variable resistor The variable resistors are two types, gradient adjustment (VRHP(N)/VRLP(N)), and amplitude adjustment (VRP(N)0/VRP(N)1). The resistances are set by the gradient adjustment and amplitude adjustment registers. Their relationship is shown below.
Gradient Adjustment (1)
Register value PRP(N)0[2:0] Resistance value VRHP(N)
Gradient Adjustment (1)
Register value PRP(N)1[2:0] Resistance value VRLP(N)
Gradient Adjustment (1)
Register value VRP(N)0[3:0] Resistance value VRP(N)0
Gradient Adjustment (1)
Register value VRP(N)1[4:0] Resistance value VRP(N)1
000 001 010 011 100 101 110 111
0R 4R 8R 12R 16R 20R 24R 28R
000 001 010 011 100 101 110 111
0R 4R 8R 12R 16R 20R 24R 28R
0000 0001 0010 : : 1101 1110 1111
0R 1R 2R : : 13R 14R 15R
00000 00001 00010 : : 11101 11110 11111
0R 1R 2R : : 29R 30R 31R
Rev.1.11, Oct. 02.2003, page 126 of 175
HD66776 8 to 1 selector In the 8 to 1 selector, the voltage level can be selected from the levels which are generated by ladder resistors, and be output the six types of the reference voltage, the VIN1 to VIN6. The following figure explains the relationship between the fine adjustment register and the selecting voltage. KVPP and KVPN
Contents of Register PKP(N)2-0 000 001 010 011 100 101 110 111 Selected Voltage VINP(N)1 KVP(N)1 KVP(N)2 KVP(N)3 KVP(N)4 KVP(N)5 KVP(N)6 KVP(N)7 KVP(N)8 VINP(N)2 KVP(N)9 KVP(N)10 KVP(N)11 KVP(N)12 KVP(N)13 KVP(N)14 KVP(N)15 KVP(N)16 VINP(N)3 KVP(N)17 KVP(N)18 KVP(N)19 KVP(N)20 KVP(N)21 KVP(N)22 KVP(N)23 KVP(N)24 VINP(N)4 KVP(N)25 KVP(N)26 KVP(N)27 KVP(N)28 KVP(N)29 KVP(N)30 KVP(N)31 KVP(N)32 VINP(N)5 KVP(N)33 KVP(N)34 KVP(N)35 KVP(N)36 KVP(N)37 KVP(N)38 KVP(N)39 KVP(N)40 VINP(N)6 KVP(N)41 KVP(N)42 KVP(N)43 KVP(N)44 KVP(N)45 KVP(N)46 KVP(N)47 KVP(N)48
Rev.1.11, Oct.02.2003, page 127 of 175
HD66776 The grayscale levels V0~V63 are calculated by the following formula. Voltage formula (positive polarity)
Pins KVP0 KVP1 KVP2 KVP3 KVP4 KVP5 KVP6 KVP7 KVP8 KVP9 KVP10 KVP11 KVP12 KVP13 KVP14 KVP15 KVP16 KVP17 KVP18 KVP19 KVP20 KVP21 KVP22 KVP23 KVP24 KVP25 KVP26 KVP27 KVP28 KVP29 KVP30 KVP31 KVP32 KVP33 KVP34 KVP35 KVP36 KVP37 KVP38 KVP39 KVP40 KVP41 KVP42 KVP43 KVP44 KVP45 KVP46 KVP47 KVP48 KVP49 Formula VDH- V*VRP0/SUMRP VDH- V*(VRP0+5R)/SUMRP VDH- V*(VRP0+9R)/SUMRP VDH- V*(VRP0+13R)/SUMRP VDH- V*(VRP0+17R)/SUMRP VDH- V*(VRP0+21R)/SUMRP VDH- V*(VRP0+25R)/SUMRP VDH- V*(VRP0+29R)/SUMRP VDH- V*(VRP0+33R)/SUMRP VDH- V*(VRP0+33R+VRHP)/SUMRP VDH- V*(VRP0+34R+VRHP)/SUMRP VDH- V*(VRP0+35R+VRHP)/SUMRP VDH- V*(VRP0+36R+VRHP)/SUMRP VDH- V*(VRP0+37R+VRHP)/SUMRP VDH- V*(VRP0+38R+VRHP)/SUMRP VDH- V*(VRP0+39R+VRHP)/SUMRP VDH- V*(VRP0+40R+VRHP)/SUMRP VDH- V*(VRP0+45R+VRHP)/SUMRP VDH- V*(VRP0+46R+VRHP)/SUMRP VDH- V*(VRP0+47R+VRHP)/SUMRP VDH- V*(VRP0+48R+VRHP)/SUMRP VDH- V*(VRP0+49R+VRHP)/SUMRP VDH- V*(VRP0+50R+VRHP)/SUMRP VDH- V*(VRP0+51R+VRHP)/SUMRP VDH- V*(VRP0+52R+VRHP)/SUMRP VDH- V*(VRP0+68R+VRHP)/SUMRP VDH- V*(VRP0+69R+VRHP)/SUMRP VDH- V*(VRP0+70R+VRHP)/SUMRP VDH- V*(VRP0+71R+VRHP)/SUMRP VDH- V*(VRP0+72R+VRHP)/SUMRP VDH- V*(VRP0+73R+VRHP)/SUMRP VDH- V*(VRP0+74R+VRHP)/SUMRP VDH- V*(VRP0+75R+VRHP)/SUMRP VDH- V*(VRP0+80R+VRHP)/SUMRP VDH- V*(VRP0+81R+VRHP)/SUMRP VDH- V*(VRP0+82R+VRHP)/SUMRP VDH- V*(VRP0+83R+VRHP)/SUMRP VDH- V*(VRP0+84R+VRHP)/SUMRP VDH- V*(VRP0+85R+VRHP)/SUMRP VDH- V*(VRP0+86R+VRHP)/SUMRP VDH- V*(VRP0+87R+VRHP)/SUMRP VDH- V*(VRP0+87R+VRHP+VRLP)/SUMRP VDH- V*(VRP0+91R+VRHP+VRLP)/SUMRP VDH- V*(VRP0+95R+VRHP+VRLP)/SUMRP VDH- V*(VRP0+99R+VRHP+VRLP)/SUMRP VDH- V*(VRP0+103R+VRHP+VRLP)/SUMRP VDH- V*(VRP0+107R+VRHP+VRLP)/SUMRP VDH- V*(VRP0+111R+VRHP+VRLP)/SUMRP VDH- V*(VRP0+115R+VRHP+VRLP)/SUMRP VDH- V*(VRP0+120R+VRHP+VRLP)/SUMRP Micro-adjsting register PKP02-00 = "000" PKP02-00 = "001" PKP02-00 = "010" PKP02-00 = "011" PKP02-00 = "100" PKP02-00 = "101" PKP02-00 = "110" PKP02-00 = "111" PKP12-10 = "000" PKP12-10 = "001" PKP12-10 = "010" PKP12-10 = "011" PKP12-10 = "100" PKP12-10 = "101" PKP12-10 = "110" PKP12-10 = "111" PKP22-20 = "000" PKP22-20 = "001" PKP22-20 = "010" PKP22-20 = "011" PKP22-20 = "100" PKP22-20 = "101" PKP22-20 = "110" PKP22-20 = "111" PKP32-30 = "000" PKP32-30 = "001" PKP32-30 = "010" PKP32-30 = "011" PKP32-30 = "100" PKP32-30 = "101" PKP32-30 = "110" PKP32-30 = "111" PKP42-00 = "000" PKP42-40 = "001" PKP42-40 = "010" PKP42-40 = "011" PKP42-40 = "100" PKP42-40 = "101" PKP42-40 = "110" PKP42-40 = "111" PKP52-50 = "000" PKP52-50 = "001" PKP52-50 = "010" PKP52-50 = "011" PKP52-50 = "100" PKP52-50 = "101" PKP52-50 = "110" PKP52-50 = "111" Reference VINP0
VINP1
VINP2
VINP3
VINP4
VINP5
VINP6
VINP7
SUMRP: Total of the positive polarity ladder resistance = 128R + VRHP + VRLP + VRP0 + VRP1 SUMRN: Total of th enegative polarity ladder resistance = 128R + VRHN + VRLN + VRN0 + VRN1 V: Voltage difference between VDH-VGS
Rev.1.11, Oct. 02.2003, page 128 of 175
HD66776 Voltage Formula-2 (positive polarity)
grayscale voltage V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 V32 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 V43 V44 V45 V46 V47 V48 V49 V50 V51 V52 V53 V54 V55 V56 V57 V58 V59 V60 V61 V62 V63 Formula VINP0 VINP1 V8+(V1-V8)*(30/48) V8+(V1-V8)*(23/48) V8+(V1-V8)*(16/48) V8+(V1-V8)*(12/48) V8+(V1-V8)*(8/48) V8+(V1-V8)*(4/48) VINP2 V20+(V8-V20)*(22/24) V20+(V8-V20)*(20/24) V20+(V8-V20)*(18/24) V20+(V8-V20)*(16/24) V20+(V8-V20)*(14/24) V20+(V8-V20)*(12/24) V20+(V8-V20)*(10/24) V20+(V8-V20)*(8/24) V20+(V8-V20)*(6/24) V20+(V8-V20)*(4/24) V20+(V8-V20)*(2/24) VINP3 V43+(V20-V43)*(22/23) V43+(V20-V43)*(21/23) V43+(V20-V43)*(20/23) V43+(V20-V43)*(19/23) V43+(V20-V43)*(18/23) V43+(V20-V43)*(17/23) V43+(V20-V43)*(16/23) V43+(V20-V43)*(15/23) V43+(V20-V43)*(14/23) V43+(V20-V43)*(13/23) V43+(V20-V43)*(12/23) V43+(V20-V43)*(11/23) V43+(V20-V43)*(10/23) V43+(V20-V43)*(9/23) V43+(V20-V43)*(8/23) V43+(V20-V43)*(7/23) V43+(V20-V43)*(6/23) V43+(V20-V43)*(5/23) V43+(V20-V43)*(4/23) V43+(V20-V43)*(3/23) V43+(V20-V43)*(2/23) V43+(V20-V43)*(1/23) VINP4 V55+(V43-V55)*(22/24) V55+(V43-V55)*(20/24) V55+(V43-V55)*(18/24) V55+(V43-V55)*(16/24) V55+(V43-V55)*(14/24) V55+(V43-V55)*(12/24) V55+(V43-V55)*(10/24) V55+(V43-V55)*(8/24) V55+(V43-V55)*(6/24) V55+(V43-V55)*(4/24) V55+(V43-V55)*(2/24) VINP5 V62+(V55-V62)*(44/48) V62+(V55-V62)*(40/48) V62+(V55-V62)*(36/48) V62+(V55-V62)*(32/48) V62+(V55-V62)*(25/48) V62+(V55-V62)*(18/48) VINP6 VINP7
Rev.1.11, Oct. 02.2003, page 129 of 175
HD66776 Voltage Formula (Negative polarity)
Pins KVN0 KVN1 KVN2 KVN3 KVN4 KVN5 KVN6 KVN7 KVN8 KVN9 KVN10 KVN11 KVN12 KVN13 KVN14 KVN15 KVN16 KVN17 KVN18 KVN19 KVN20 KVN21 KVN22 KVN23 KVN24 KVN25 KVN26 KVN27 KVN28 KVN29 KVN30 KVN31 KVN32 KVN33 KVN34 KVN35 KVN36 KVN37 KVN38 KVN39 KVN40 KVN41 KVN42 KVN43 KVN44 KVN45 KVN46 KVN47 KVN48 KVN49 Formula VDH- V*VRN0/SUMRN VDH- V*(VRN0+5R)/SUMRN VDH- V*(VRN0+9R)/SUMRN VDH- V*(VRN0+13R)/SUMRN VDH- V*(VRN0+17R)/SUMRN VDH- V*(VRN0+21R)/SUMRN VDH- V*(VRN0+25R)/SUMRN VDH- V*(VRN0+29R)/SUMRN VDH- V*(VRN0+33R)/SUMRN VDH- V*(VRN0+33R+VRHN)/SUMRN VDH- V*(VRN0+33R+VRHN)/SUMRN VDH- V*(VRN0+35R+VRHN)/SUMRN VDH- V*(VRN0+36R+VRHN)/SUMRN VDH- V*(VRN0+37R+VRHN)/SUMRN VDH- V*(VRN0+38R+VRHN)/SUMRN VDH- V*(VRN0+39R+VRHN)/SUMRN VDH- V*(VRN0+40R+VRHN)/SUMRN VDH- V*(VRN0+45R+VRHN)/SUMRN VDH- V*(VRN0+46R+VRHN)/SUMRN VDH- V*(VRN0+47R+VRHN)/SUMRN VDH- V*(VRN0+48R+VRHN)/SUMRN VDH- V*(VRN0+49R+VRHN)/SUMRN VDH- V*(VRN0+50R+VRHN)/SUMRN VDH- V*(VRN0+51R+VRHN)/SUMRN VDH- V*(VRN0+52R+VRHN)/SUMRN VDH- V*(VRN0+68R+VRHN)/SUMRN VDH- V*(VRN0+69R+VRHN)/SUMRN VDH- V*(VRN0+70R+VRHN)/SUMRN VDH- V*(VRN0+71R+VRHN)/SUMRN VDH- V*(VRN0+72R+VRHN)/SUMRN VDH- V*(VRN0+73R+VRHN)/SUMRN VDH- V*(VRN0+74R+VRHN)/SUMRN VDH- V*(VRN0+75R+VRHN)/SUMRN VDH- V*(VRN0+80R+VRHN)/SUMRN VDH- V*(VRN0+81R+VRHN)/SUMRN VDH- V*(VRN0+82R+VRHN)/SUMRN VDH- V*(VRN0+83R+VRHN)/SUMRN VDH- V*(VRN0+84R+VRHN)/SUMRN VDH- V*(VRN0+85R+VRHN)/SUMRN VDH- V*(VRN0+86R+VRHN)/SUMRN VDH- V*(VRN0+87R+VRHN)/SUMRN VDH- V*(VRN0+87R+VRHN+VRLN)/SUMRN VDH- V*(VRN0+91R+VRHN+VRLN)/SUMRN VDH- V*(VRN0+95R+VRHN+VRLN)/SUMRN VDH- V*(VRN0+99R+VRHN+VRLN)/SUMRN VDH- V*(VRN0+103R+VRHN+VRLN)/SUMRN VDH- V*(VRN0+107R+VRHN+VRLN)/SUMRN VDH- V*(VRN0+111R+VRHN+VRLN)/SUMRN VDH- V*(VRN0+115R+VRHN+VRLN)/SUMRN VDH- V*(VRN0+120R+VRHN+VRLN)/SUMRN Micro-adjsting register PKN02-00 = "000" PKN02-00 = "001" PKN02-00 = "010" PKN02-00 = "011" PKN02-00 = "100" PKN02-00 = "101" PKN02-00 = "110" PKN02-00 = "111" PKN12-10 = "000" PKN12-10 = "001" PKN12-10 = "010" PKN12-10 = "011" PKN12-10 = "100" PKN12-10 = "101" PKN12-10 = "110" PKN12-10 = "111" PKN22-20 = "000" PKN22-20 = "001" PKN22-20 = "010" PKN22-20 = "011" PKN22-20 = "100" PKN22-20 = "101" PKN22-20 = "110" PKN22-20 = "111" PKN32-30 = "000" PKN32-30 = "001" PKN32-30 = "010" PKN32-30 = "011" PKN32-30 = "100" PKN32-30 = "101" PKN32-30 = "110" PKN32-30 = "111" PKN42-00 = "000" PKN42-00 = "001" PKN42-00 = "010" PKN42-00 = "011" PKN42-00 = "100" PKN42-00 = "101" PKN42-00 = "110" PKN42-00 = "111" PKN52-50 = "000" PKN52-50 = "001" PKN52-50 = "010" PKN52-50 = "011" PKN52-50 = "100" PKN52-50 = "101" PKN52-50 = "110" PKN52-50 = "111" Reference VINN0
VINN1
VINN2
VINN3
VINN4
VINN5
VINN6
VINN7
SUMRP: Total of the positive polarity ladder resistance = 128R + VRHP + VRLP + VRP0 + VRP1 SUMRN: Total of th enegative polarity ladder resistance = 128R + VRHN + VRLN + VRN0 + VRN1 V: Voltage difference between VDH-VGS
Rev.1.11, Oct. 02.2003, page 130 of 175
HD66776 Voltage formula -2 (Negative formula)
grayscale voltage V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 V32 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 V43 V44 V45 V46 V47 V48 V49 V50 V51 V52 V53 V54 V55 V56 V57 V58 V59 V60 V61 V62 V63 Formula VINN0 VINN1 V8+(V1-V8)*(30/48) V8+(V1-V8)*(23/48) V8+(V1-V8)*(16/48) V8+(V1-V8)*(12/48) V8+(V1-V8)*(8/48) V8+(V1-V8)*(4/48) VINN2 V20+(V8-V20)*(22/24) V20+(V8-V20)*(20/24) V20+(V8-V20)*(18/24) V20+(V8-V20)*(16/24) V20+(V8-V20)*(14/24) V20+(V8-V20)*(12/24) V20+(V8-V20)*(10/24) V20+(V8-V20)*(8/24) V20+(V8-V20)*(6/24) V20+(V8-V20)*(4/24) V20+(V8-V20)*(2/24) VINN3 V43+(V20-V43)*(22/23) V43+(V20-V43)*(21/23) V43+(V20-V43)*(20/23) V43+(V20-V43)*(19/23) V43+(V20-V43)*(18/23) V43+(V20-V43)*(17/23) V43+(V20-V43)*(16/23) V43+(V20-V43)*(15/23) V43+(V20-V43)*(14/23) V43+(V20-V43)*(13/23) V43+(V20-V43)*(12/23) V43+(V20-V43)*(11/23) V43+(V20-V43)*(10/23) V43+(V20-V43)*(9/23) V43+(V20-V43)*(8/23) V43+(V20-V43)*(7/23) V43+(V20-V43)*(6/23) V43+(V20-V43)*(5/23) V43+(V20-V43)*(4/23) V43+(V20-V43)*(3/23) V43+(V20-V43)*(2/23) V43+(V20-V43)*(1/23) VINN4 V55+(V43-V55)*(22/24) V55+(V43-V55)*(20/24) V55+(V43-V55)*(18/24) V55+(V43-V55)*(16/24) V55+(V43-V55)*(14/24) V55+(V43-V55)*(12/24) V55+(V43-V55)*(10/24) V55+(V43-V55)*(8/24) V55+(V43-V55)*(6/24) V55+(V43-V55)*(4/24) V55+(V43-V55)*(2/24) VINN5 V62+(V55-V62)*(44/48) V62+(V55-V62)*(40/48) V62+(V55-V62)*(36/48) V62+(V55-V62)*(32/48) V62+(V55-V62)*(25/48) V62+(V55-V62)*(18/48) VINN6 VINN7
Rev.1.11, Oct. 02.2003, page 131 of 175
HD66776 Relation between RAM Data and Output level
V0
Negative polarity
Output level
V63
Positive polarity
000000
RAM data (Common characteristics to RGB)
111111
Relat ionship between RAM data and output level ( REV = 0)
V0 Negative polarity Output level
Positive polarity V63 111111 RAM data (Common characteristics to RGB) 000000
Relat ionship between RAM data and output level ( REV =1)
Sn
Negative polarity Vcom Positive polarity
Relations hip be tw een Sourc e Output a nd V com
Rev.1.11, Oct. 02.2003, page 132 of 175
HD66776
8-Color Display Mode
The HD66776 incorporates an 8-color display mode as low power consumption display mode. The grayscale level to be used is indicated below, and the unused levels are stopped. This, therefore, achieved to reduce the power consumption.
COL 0 1 Number of display color 262,144 8
Active amplifer on each mode (n Where amplifier is active.)
Number of display color 262K 8 Number of display color 262K 8 RAM data
Amplifier
RAM data
Amplifier
V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31
n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n
n
111111 111110 111101 111100 111011 111010 111001 111000 110111 110110 110101 110100 110011 110010 110001 110000 101111 101110 101101 101100 101011 101010 101001 101000 100111 100110 100101 100100 100011 10010 100001 100000
V32 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 V43 V44 V45 V46 V47 V48 V49 V50 V51 V52 V53 V54 V55 V56 V57 V58 V59 V60 V61 V62 V63
n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n n
n
011111 011110 011101 011100 011011 011010 011001 011000 010111 010110 010101 010100 010011 010010 010001 010000 001111 001110 001101 001100 001011 001010 001001 001000 000111 000110 000101 000100 000011 000010 000001 000000
Rev.1.11, Oct. 02.2003, page 133 of 175
HD66776 When HD66776 is operated in low power consumption mode, the process below is executed while RAM data writing, and HD66776 automatically selects the active amplifier.
n 18-bit interface mode
8-color mode
Input pin DB 17 DB DB 16 15 DB DB DB 14 13 12 DB DB DB 11 10 9 DB DB 8 7 DB 6 DB 5 DB 4 DB DB 3 2 DB 1 DB 0
RAM data
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB pixel assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
n 16-bit interface mode
8-color mode
Input pin DB 17 DB DB 16 15 DB DB DB 14 13 12 DB DB 11 10 DB DB 8 7 DB 6 DB 5 DB 4 DB DB 3 2 DB 1
RAM data
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB pixel assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Rev.1.11, Oct. 02.2003, page 134 of 175
HD66776
n 9-bit interface mode 8-color mode
First transfer (upper)
Input pin DB DB 17 16 DB 15 DB 14 DB DB 13 12 DB 11 DB DB 10 9
DB DB 17 16
Second transfer (lower)
DB 15 DB DB 14 13 DB 12 DB 11 DB DB 10 9
RAM data
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB pixel assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
n 8-bit interface mode 8-color mode
First transfer (upper)
Input pin DB DB 17 16 DB 15 DB 14 DB DB 13 12 DB 11 DB 10
Second transfer (lower)
DB DB DB 17 16 15 DB DB 14 13 DB 12 DB DB 11 10
RAM data
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB pixel assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Rev.1.11, Oct. 02.2003, page 135 of 175
HD66776
n 8-bit interface mode (2) 8-color mode
First transfer Second transfer Third transfer
Input pin
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB 11 10 17 16 15 14 13 12 11 10 17 16 15 14 13 12 11 10
RAM data WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB pixel assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
n 8-bit interface mode (3) 8-color mode
First transfer Input pin
DB DB DB DB DB DB 17 16 15 14 13 12
Second transfer
DB DB DB DB DB DB 17 16 15 14 13 12
Third transfer
DB DB DB DB DB DB 17 16 15 14 13 12
RAM data WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB pixel assignment R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Rev.1.11, Oct. 02.2003, page 136 of 175
HD66776
n RGB interface 18-bit)mode ( 8-color-mode
Input pin PD PD PD PD PD PD PD PD PD 17 16 15 14 13 12 11 10 9 PD PD PD 8 7 6 PD PD 5 4 PD PD PD 3 2 1 PD 0
RAM data
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB pixel assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
n RGB interface 16-bit)mode ( 8-color-mode
Input pin
PD PD PD PD PD PD PD PD 17 16 15 14 13 12 11 10
PD PD PD 8 7 6
PD PD 5 4
PD PD PD 3 2 1
RAM data
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB pixel assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
n RGB interface (9 -bit) m ode
8-color-mode
First transfer (upper)
Input pin PD PD PD PD PD PD PD PD PD 17 16 15 14 13 12 11 10 9
Second transfer (lower)
PD PD PD PD PD PD PD PD PD 17 16 15 14 13 12 11 10 9
RAM data
WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD WD 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB pixel assignment
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
Rev.1.11, Oct. 02.2003, page 137 of 175
HD66776
Example of System Configuration of TFT display
The following diagram indicates a connection example of HD66776 and HD667P20 (power supply IC) when consisting the 256RGB x 320dot poly-silicon TFT-LCD panel with internal gate driver's System Configuration of TFT display
* Input control signals according to the input siganl lines to poly-silicon TFT.
G1 G2 Internal Gate driver G319 G320 S1 S2 Internal RGB selecting sw itch
4
SOUT1 to 4
Poly-silicon TFT-LCD ((240 x 3) x 320)
3 2
S719, S720
CLAO, CLBO, CLCO VGH, VGL
Vcom 3
GCS*, GDA, GCL M DCCLK Vcom VDH DDVDH RESET* 5
HD66776
3
SOUT1 to SOUT4 SIN1 to SIN4, RESET* EQ CLA, CLB, CLC
FLM, SFTCLK2, SFTCLK1, DISPTMG, EQ, CLA, CLB, CLC RESET
CLAO, CLBO, CLCO
VREG1OUT Vcom DDVDH GCS*, GDA, GCL
M DCCLK
16
4
3 Vcc GND IM2, IM1, IM0/ID
DB0 to DB15 RESET
CS*, WR*, RD*, RS
HD667P20
Vcc,Vci GND
Rev.1.11, Oct. 02.2003, page 138 of 175
HD66776
When using 80 system 18 bits interface
To panel opposed electrode
TEST GNDDUM2 IM3 IM2 IM1 IM0 VccDUM1 OSC3 OSC2 OSC1 Vcom Vcom DDVDH
Example of Chip set connecting
Example of COG mounting
HD66776
DDVDH VDH VGS V63N V63P V0N V0P VDDTEST VRTEST AGND AGND GND GND VDD2 VDD2 VDD1 VDD1 VREF Vci Vci VCC
240 x 320 (QVGA)
PD17-0 ENABLE DOTCLK HSYNC VSYNC
CS* RS WR* RD* DB17-0 RESET
Connect on FPC
HD66766 (Bottom View)
HD667P20
Poly silicon TFT Panel
Rev.1.11, Oct. 02.2003, page 139 of 175
VCC PD17-0 ENABLE DOTCLK HSYNC VSYNC GNDDUM1 VLD CS* RS WR* RD* DB17-0 RESET DCCLK1 GCL1 GCS1* GDA1 DISPTMG1 EQ1 M1 SFTCLK11 SFTCLK21 FLM1 CLA1 CLB1 CLC1 RESET01*
DMY6 DCCLK GCL GCS* GDA SIN4 EQ GNDDMY2 VCCDMY1 TESTT M GNDDMY1 SIN3 SIN2 SIN1 CLA CLB CLC RESET* TESTS DMY5
DMY4
When not using EQ
DMY7
VCC/Vci
DMY6 DCCLK GCL GCS* GDA SIN4 EQ GNDDMY2 VCCDMY1 TESTT M GNDDMY1 SIN3 SIN2 SIN1 CLA CLB CLC RESET* TESTS DMY5
GND
DMY8 DMY9 DMY10 DMY11 DMY12 GNDDMY3 GNDDMY4 GNDDMY5 TESTM TESTL TESTG VCCDMY2 VCCDMY3 VTEST TESTV4
DMY13 DMY14 DMY15 DMY16 DMY17 DMY18 DMY19 DMY20 DMY21 DMY22 DMY23 DMY24 DMY25 DMY26 DMY27 DMY28 DMY29
To panel opposed
Figure indicates the example of connection between source driver HD66776 and power supply IC HD667P20.
HD667P20 (Bottom View)
Gate cirucit
DMY3 Vci Vci Vci Vci Vci VCC VCC GND GND GND GND GND GND VciOUT Vci1 Vci1 VCOMR VREG1 VREG1OUT VLOUT1 DDVDH DDVDH DDVDH VLOUT2 VLOUT2 VGH VGH VCOMH VCOMH VCOML VCOML VCL VCL VLOUT4 VLOUT3 VLOUT3 VLOUT3 VGL VGL C11C11C11C11C11+ C11+ C11+ C11+ C12C12C12C12+ C12+ C12+ C21C21C21+ C21+ C22C22C22+ C22+ DMY2
DMY2
Vcom Vcom CLCO CLBO CLAO TESTV3 TESTV2 TESTV1 SOUT4 SOUT3 SOUT2 SOUT1 SOUT1 DMY30 DMY31 DMY32 DMY33 DMY34 DMY35
2002/10/02
DMY36 DMY37 DMY38 DMY39 DMY40 DMY41 DMY42 DMY43 DMY44 DMY45 TESTA1 TESTA2 TESTA4 TESTA5 TESTA6 TESTR TDCB TDCA Vcom Vcom DMY46
M.Yamagami
HD66776
Instruction Setting Flow
The following chart is the example of setting instructions for starting up HD66776/HD667P10. The instruction setting for the HD67P10 is executed by the serial interface. Execute the serial transfer command right after setting the instruction of HD66776.
[Power supply ON]
[Display ON] Display OFF
Power supply OFF Vcc, Vci ON Hardware reset More than 1ms Oscillation start
Clock initial setting
nHD66776 FW, FT setting SW, ST setting CLW, CLT setting DPW, DPT setting MCP setting SH setting
Display ON More than 10ms
nHD66776 control setting DC4-3, 2-0 setting nHD667P20 AP2-0 = "000" VCOMG = "0" PON = "0" VC2-0 bit setting VRH3-0 bit setting VCM4-0 bit setting VDV4-0 bit setting VGH4-0 bit setting VGL4-0 bit setting DK1-0 = "01" Serial transfer nHD667P20 DC2-0 setting BT2-0 setting AP2-0 setting PON = "1" Serial transfer nHD667P20 DK1-0 = "00" Serial transfer nHD667P20 SAP2-0 bit setting
nHD66776 D1-0 = "01" DTE = "0" GON = "0"
Power supply initial setting
Wait (More than two frames) Display ON
nHD66776 D1-0 = "01" DTE = "0" GON = "1"
Serial transfer Display ON
nHD66776 D1-0 = "11" DTE = "0" GON = "1"
Power supply start up setting (1) More than 30ms Power supply start up setting (2) More than 10ms Source operation setting More than 10ms Power supply start up setting (3) Other mode setting More than 60ms
Wait (More than two frames) Display ON
nHD66776 D1-0 = "11" DTE = "1" GON = "1"
Display ON
nHD667P20 VCOMG = "1" Serial transfer nHD66776 Mode setting RAM setting nHD667P20 Serial transfer
Display ON sequence
Rev.1.11, Oct. 02.2003, page 140 of 175
HD66776
[ Display OFF]
[Power supply OFF]
Display ON
Display OFF
Equalize OFF
n HD66776 EQWI = "0", EQWE = "0"
Power off setting
Display OFF
n HD66776 D1-0 ="10" DTE = "1" GON = "1"
n HD66776 SAP2-0 ="000" n HD667P20 AP2-0 = "000" VCOMG = "0" PON = "0" Serial transfer
Serial transfer
Wait (more than two frames) Display OFF
n HD66776 D1-0 ="10" DTE = "0" GON = "1"
Display OFF
Wait (more than two frames)
Power ON sequece
Display OFF
n HD66776 D1-0 ="00" DTE = "0" GON = "0"
Serial transfer
Display OFF
Power OFF sequence
Rev.1.11, Oct. 02.2003, page 141 of 175
HD66776
Sleep
Display ON
Stand-by
Display ON
Display off sequence Stand-by set Power supply off sequence Stand-by setting
n HD66776
STB = "1"
Display off sequence
Power supply off sequence
Sleep set
Sleep setting Serial transfer
n HD66776
SLP ="1"
Stand-by
n HD66776
Sleep
Oscillation start
More than 10ms
Oscillation start Stand-by setting cancellation
Sleep cancellation
n HD66776
SLP = "0"
Stand-by cancellation Power supply on sequence
n HD66776
STB = "0"
Sleep cancellation Power supply on sequence
Display on sequence
Display on sequence
Display ON
Display ON
Rev.1.11, Oct. 02.2003, page 142 of 175
HD66776
[ Deep Stand-by]
Display ON
Display off sequence
Power supply off sequence
Deep stand-by set
n HD66776 DSTB ="1"
Deep stand-by setting
Deep stand-by
Cancellation of deep stand-by (1)
More than1ms
n HD66776 CS ="L" n HD66776 CS ="L" nHD66776 CS ="L" nHD66776 CS ="L" nHD66776 CS ="L" nHD66776 CS ="L"
Cancellation of deep stand-by (2)
Cancellation of deep stand-by (3)
Cancellation of deep stand-by (4)
Cancellation of deep stand-by (5)
Cancellation of deep stand-by (6)
Deep stand-by cancellation
Cancellation of deep standby is completed through "Cancellation of deep stand-by (1) to (5). And during the cancellation period, its inside is unstable. Cancellation must be executed consecutively from (1) to (6).
Power supply initial setting
Power supply start up setting (1)
Refer to the power on sequence
Power supply start up setting (2)
Other mode setting
Display on sequence
Cancellation of Deep stand-by mode (1)
Cancellation of Deep stand-by mode (2)
Cancellation of Deep stand-by mode (3)
Cancellation of Deep stand-by mode (4)
Cancellation of Deep stand-by mode (5)
Cancellation of Deep stand-by mode (6)
t1 CS
t2
t1
t2
t1
t2
t1
t2
t1
t2
t1
t2
t1:45ns (min.) t2:25ns (min.)
1ms (min.)
Rev.1.11, Oct. 02.2003, page 143 of 175
HD66776
[262,144 to 8 color mode color mode] [8 color mode to 262,144 color mode] 262,144 color Display
Display OFF
n
HD66776 DI-0 = "10" DTE = "1" GON = "1"
Wait (more than two frames) COL setting More than 10ms RAM setting Display ON
n
HD66776 COL = "1"
n
HD66776 RAM write HD66776 D1-0 ="11" DTE = "1" GON = "1"
n
8 color Display
Display OFF
n
HD66776 D1-0 ="10" DTE = "1" GON = "1"
Wait (more than two frames) COL setting More than 10ms RAM setting Display ON
n
HD66776 COL = "0"
n
HD66776 RAM write HD66776 D1-0 = "11" DTE = "1" GON = "1"
n
262,144 color Display
Rev.1.11, Oct. 02.2003, page 144 of 175
HD66776
[Partial display] Full display
Partial setting
n HD66776 PT1-0 = "00"
Display drive osition setting
n HD66776 SS18-10, SE18-10 bit setting SS28-10, SE28-10 bit setting SPT-bit setting
Wait more than two frames
Set if necessary HD66776 PT109 ="01" or "10" or "11"
n
Partial setting
Partial display
n HD66776 SS18-10, SE18-10 bit setting SPT ="0"
Display drive powition setting
Full display
Rev.1.11, Oct. 02.2003, page 145 of 175
HD66776
[ Internal clock operation to VSYNC interface]
[ VSYNC interface to Internal clock operation ]
Internal clock operation
VSYNC operation
High-spee write mode setting d
n HD66776
HWM1-0 = " 11", AM = "0"
Internal clock mode settin n HD66776 g
DM1-0 = "00", RM = "0"
Address se tting
nHD66776 nHD66776
Wait (more than 1 frame)
AD16-0 se tting
VSYNC mode setting
DM1-0 = "10", RM = "0"
Internal clock operation
Wait (more than 1 frame)
VSYNC interface RAM write
VSYNC operation
Rev.1.11, Oct. 02.2003, page 146 of 175
HD66776
[Internal clock operation to RGB interface (1)]
[RGB interface (1) to Internal clock operation] RGB interface operation
Internal clock operation
High-speed write mode setting
nHD66776 HWM1-0 = "11", AM = "0" n HD66776 AD16-0 setting n HD66776 DM1-0 = "01", RM = "1"
Internal clock mode setting
n HD66776 DM1-0 = "00", RM = "0"
Address setting
Wait (more than 1 frame)
RGB mode setting
Internal clock operation
Wait (more than 1 frame)
RGB interface RAM write
RGB interface operation
Rev.1.11, Oct. 02.2003, page 147 of 175
HD66776 RAM data writing flow from system interface displaying RGB interfaced.
[ RGB interface (1) to RGB interface (2) ]
RGB interface operation
[ RGB interface (2) to RGB interface (1) ]
System interface RAM write
n HD66776 HWM1-0 = "11", AM = "0" n HD66776 AD17-0 setting
RGB mode setting
n HD66776 DM1-0 = "01", RM = "0" n HD66776 HWM = "0" or "1"
High-speed write mode setting
Write mode setting
Address setting
Address setting
n HD66776 AD16-0 setting
RGB mode setting
n HD66776 DM1-0 = "01", RAM = "1"
System interface RAM write
RGB interface operation
Rev.1.11, Oct. 02.2003, page 148 of 175
HD66776
Oscillation circuit
The HD66776 can oscillate between the OSC1 and OSC2 pins using an internal R-C oscillator with an external oscillation resistor. Note that in R-C oscillation, the oscillation frequency is changed according ot the external resistance value, writing length, or operating power-supply voltage. If Rf is increased or power supply voltage is decreases, the oscillation frequency decreases. For the relation ship between Rf resistor value and oscillation frequency, see the Electric Characteristics Notes section.
OSC1 Rf OSC2 HD66776
Note) The Rf resistance must be located near the OSC1/OSC2 pin.
Rev.1.11, Oct. 02.2003, page 149 of 175
HD66776
n-raster-row Reversed AC Drive
The HD66776 supports not only the LCD reversed AC drive in a one-frame unit but also the n-raster-row reversed AC drive which alternates in an n-raster-row unit from one to 64-raster-rows. When a problem affecting display quality occurs, the n-raster-row reversed AC drive can improve the quality. Determine the number of the raster-rows n (NW bit set value+1) for alternating after confirmation of the display quality with the actual LCD panel. However, if the number of AC raster-row is reduced, the LCD alternating frequency becomes high. Because of this, the charge of discharge current is increased in the LCD cells.
1 frame
Back porch 1 2 3 4 321 322 Front porch 336 Back porch 1 2 3 4
1 frame
Front porch 321 322 336 1 2
Frame AC wave-form drive 320 raster-row
n-raster-row AC wave-form drive 320 raster-row reverse 3 raster-row EOR="1"
Note: In an n-raster-row driving EOR should be "1" so that DC bias voltage is not applied.
Example of an AC Signal under n-raster-row Reversed AC Drive
Rev.1.11, Oct. 02.2003, page 150 of 175
HD66776
AC Drive Timing
Following diagram indicates the timing of changing polarity on the each A/C drive method. LCD drive polarity is changed after every frame. After the A/C this timing, the blank (all outputs from the gate Vgoff output) in 4 to 16H period is inserted. When the reversed n-raster-row is driving, a blank period of the 4 to 16H periods is inserted after all screens are drawn.
Frame reverse AC drive A/C A/C Back porch A/C A/C Back porch n-raster-row n-raster-row n-raster-row n-raster-row n-raster-row n-raster-row n-raster-row Front porch n-raster-row reversed AC drive
1 frame period
Frame 1
A/C A/C A/C A/C A/C
AC timing Front porch
A/C Blank period =4 to 16H period
Blank period = Front + back porch = 4 to 16H period
Rev.1.11, Oct. 02.2003, page 151 of 175
1 frame period
A/C A/C
n-raster-row
HD66776
Frame Frequency Adjusting Function
The HD66776 has an on-chip frame-frequency adjustment function when it selects the internal clock action mode. The frame frequency can be adjusted by the instruction setting (DIVI, RTNI) during the LCD driver as the oscillation frequency is always same. If the oscillation frequency is set to high, animation or a static image can be displayed in suitable ways by changing the frame frequency. When a static image is displayed, the frame frequency can be set low and the low-power consumption mode can be entered. When high-speed screen switching for an animated display, etc. is required, the frame frequency can be set high. Relationship between LCD Drive Duty and Frame Frequency The relationship between the LCD drive duty and the frame frequency is calculated by the following expression. The frame frequency can be adjusted in the 1H period adjusting bit (RTNI) and in the operation clock division bit (DIVI) by the instruction. (Formula for the frame frequency) Frame Frequency = fosc Clock cycles per raster-row x division ratio x (Line + FP+BP) fosc: R-C oscillation frequency Line: Numbers of raster-rows (NL bit) Clock cycles per raster-row: RTN bit Division ratio: DIV bit FP: Front porch BP: Back porch Example of Calculation In case of maximum frame frequency = 60 Hz: Driver raster-row: 320 1H periods 16 clock (RTN3 to 0 = "10000") Operation clock division ratio:1 division fosc = 60Hz x 16 clock x 1 division x (320 +16) lines = 323[kHz] In this case, the CR oscillation frequency becomes 323 kHz. The external resistance value of the R-C oscillator must be adjusted to be 323 kHz. [Hz]
Rev.1.11, Oct. 02.2003, page 152 of 175
HD66776
Screen-division Driving Function
The HD66776 can select and drive two screens at arbitrary positions with the screen-driving position registers (R402 to R405). Any two screens required for display are selectively driven and reducing LCDdriving voltage and power consumption. For the 1st division screen, start lies (SS18 to 10) and end lines (SE18 to 10) are specified by the 1st screen-driving position register (R402 and R403). For the 2nd division screen, start line (SS28 to 20) and end lines (SE28 to 20) are specified by the 2nd screen-driving position register (R404 and R405). The 2nd screen control is effective when the SPT bit is 1. The total count of selection -driving lines for the 1st and 2nd screens must be the number of LCD drive raster-rows or less.
G1 G7
1st screen: 7raster-row driving
Non-display area
G26
2nd screen: 17raster-row driving
G42
Non-display area
Driving raster-row: NL5-0="100111" (320 lines) 1st screen setting: SS18-10 = "00"H, SE18-10 = "06H" 2nd screen setting: SS28-20 = "19"H, SE28-20 = "29"H, SPT = "1"
Display Example of Two-Screen Division Driving
It is possible to set the driver output of non-display area during partial display. Select the setting value according to the characteristic of LCD panel.
PT1 0 0 1 1 PT0 0 1 0 1 Source output of non-display area V63 V63 GND Hi-z V0 V0 GND Hi-z DISPTMG output of non-display are Normal operation "Low" "Low" "Low"
Rev.1.11, Oct. 02.2003, page 153 of 175
HD66776
Restrictions on the 1st/2nd Screen Driving Position Register Settings
The following restrictions must be satisfied when setting the start line(SS18 to 10) and end line (SE18 to 10) of the 1st screen driving position register (R402, R403) and the start line (SS28 to 20) and end line (SE 28 to 20) of the 2nd screen driving position register (R404, R405) for the HD66776. Note that incorrect display may occur if the restrictions are not satisfied. Restrictions on the 1st /2nd Screen Driving Position Register Settings 1st Screen Driving (SPT = 0)
Register setting (SE18 to 10) - (SS18 to 10) = NL (SE18 to 10) - (SS18 to 10) < NL Display operation Full screen display Normally displays (SE18 to 10) to (SS18 to 10) Partial display Normally displays (SE18 to 10) to (SS18 to 10) RAM data in other areas are not displayed. (SE18 to 1) - (SS18 to 10) > NL Note 1: SS18 to 10 <= SE18 to 10 <= "13F"H Note 2: Setting SE28 to 20 and SS28 to 20 are invalid. Setting disabled
2nd Screen Driving (SPT = 1)
Register setting ((SE18 to 10) - (SS18 to 10)) + ((SE28 to 20) - (SS28-20)) = NL ((SE18 to 10) - (SS18 to 10)) + ((SE28 to 20) - (SS28 to 20)) < NL ((SE18 to 10) - (SS18 to 10)) + ((SE28 to 20) - (SS28 to 20)) > NL Display operation Full screen display Normally displays (SE27 to 10) to (SE17 to 10) Partial display Normally displays (SE27 to 20) to (SS17 to 10) RAM data in other areas are not displayed. Setting disabled
Note 1: SS18 to 10 <= SE18 to 10 < SS28 to 20 <= SE28 to 20 <= "13F"H Note 2: (SE28 to 20) - (SS18 to 10) <= NL
Rev.1.11, Oct. 02.2003, page 154 of 175
HD66776
Absolute Maximum Ratings
Item Power supply voltage (1) Power supply voltage (2) Power supply voltage (3) Input voltage Operating temperature Storage temperature Symbol Vcc Vci DDVDH-GND Vt Topr Tstg Unit V V V V C C Value -0.3 to + 4.6 -0.3 to + 4.6 -0.3 to + 6.5 -0.3 to Vcc + 0.3 -40 to + 85 -55 to + 110 Notes 1, 2 1, 3 1, 4 1 1, 5 1, 6
Notes: 1. If the LSI is used above these absolute maximum ratings, it may become permanently damaged. Using the LSI within the following electrical characteristic limit is strongly recommended for normal operation. If these electrical characteristic conditions are also exceeded, the LSI will malfunction and cause poor reliability. 2. Vcc GND must be maintained. 3. Vci GND must be maintained. 4. DDVDH GND must be maintained. 5.For die and wafer products, specified up to 85 C.
Rev.1.11, Oct. 02.2003, page 155 of 175
HD66776
DC Characteristics (Vcc= 2.2 to 3.3V, Ta = -40 to +85oC*1)
Item Input high voltage Input low voltage (1) Output high voltage Output low voltage (1) I/O leakage current Symbol Unit Test Condition VIH VIL VOH1 VOL1 ILi V V V V A VCC = 2.2 to 3.3 V VCC = 2.2 to 3.3 V IOH = -0.1 mA VCC = 2.2 to 3.3 V, IOL = 0.1 mA Vin = 0 to VCC R-C oscillation; fosc = 325kHz (320line) A VCC = 3V, Ta = 25C, RAM data 0000h Stand-by IST mode Deep stand-by IDST mode Current Normal ICIOP consumption operation mode (2) (Vcc-GND) Stand-by ICIST mode Deep stand-by ICIDST mode LCD Power Current (DDVDH-GND) ILCD A A Vcc = 3V, Ta<=25C -- 0.1 5 5 A A Vcc = 3V, Ta>50C R-C oscillation; fosc = 325kHz (320line) VCC = 3V, Ta = 25C, RAM data 0000h Vci = 3V, Ta<=25C -- 30 100 5 -- -- 0.1 140 210 5, 6 5 5 -- 70 130 5,6 Min Typ Max VCC Notes 2, 3 0.8 VCC -- -0.3 --
0.2VCC 2, 3 -- 2
0.75VCC -- -- -1 -- --
0.2 VCC 2 1 4
Current Normal consumption operation IOP (1) mode (Vcc-GND)
A A
Vci = 3V, Ta<=25C
--
0.1 600
5 1000
5 5,6
Vcc=3V, VLCD=5.5V, VDH=5.0V, -- CR Oscillation; fosc=325kHz(320line), Ta=25C, RAMdata:0000h, REV= "0", SAP= "001", VRN4-0= "0", VRP4-0 = "0" PKP52-00 ="0", PRP12-00 = "0", VRP14-00 = "0", PKN52-00 = "0", PRN12-00 = "0", VRN14-00 = "0"
LCD Driving Voltage (DDVDH-GND) Output Voltage deviation Variation of average output voltage
VLCD Vo V
V mV mV

4.0 -- --
-- 3 --
5.9 -- 35
7 8
Rev.1.11, Oct. 02.2003, page 156 of 175
HD66776
AC Characteristic (Vcc =2.2 to 3.3V, Ta = -40oC to +85oC )
Clock Characteristics (Vcc = 2.2 to 3.3V)
Item Clock operation frequency R-C oscillation clock Symbol fcp fOSC Unit kHz kHz Test Condition VCC = 2.2 to 3.3 V Rf = 130k, Vcc = 3.0V Min 100 352 Typ 440 Max 600 528 9 Notes
80-system Bus Interface Timing Characteristics (1) 80-system 18/16/9-bit, 80-system 8-bit (TRI = 0) Normal Write mod e(HWM1-0 = 00) (Vcc = 2.2V to 3.3V during operation)
Item Bus cycle time Write Read Symbol Unit tCYCW tCYCR PWLW PWLR PWHW PWHR ns ns ns ns ns ns Test Condition Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Min 250 500 25 250 70 200 -- 15 15 25 10 25 10 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 -- -- -- -- -- -- 200 --
Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write/Read rise/fall time Setup time (RS to CS*,WR*, RD*) Address hold time VLD setup time VLD hold time Write data set up time Write data hold time Read data delay time Read data hold time
tWRr, WRf ns tAS tAH tVS tVH tDSW tH tDDR tDHR ns ns ns ns ns ns ns ns
Rev.1.11, Oct. 02.2003, page 157 of 175
HD66776 High-speed Write mode (HWM1-0 = 11) (Vcc = 2.2V to 3.3V during operation)
Item Bus cycle time Write Read Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write/Read rise/fall time Setup time (RS to CS*,WR*, RD*) Address hold time VLD setup time VLD hold time Write data set up time Write data hold time Read data delay time Read data hold time Symbol Unit tCYCW tCYCR PWLW PWLR PWHW PWHR ns ns ns ns ns ns Test Condition Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Min 250 500 25 250 35 200 -- 15 15 20 10 20 10 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 -- -- -- -- -- -- 200 --
tWRr, WRf ns tAS tAH tVS tVH tDSW tH tDDR tDHR ns ns ns ns ns ns ns ns
Rev.1.11, Oct. 02.2003, page 158 of 175
HD66776 80-system Bus Interface Timing Characteristics (2) 80-system 8-bit, (TRI = 1) Normal Write mode (HWM1-0 = 00) (Vcc = 2.2V to 3.3V during operation)
Item Bus cycle time Write Read Symbol Unit tCYCW tCYCR PWLW PWLR PWHW PWHR ns ns ns ns ns ns Test Condition Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Min 250 500 25 250 70 200 -- 20 20 25 10 25 10 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 -- -- -- -- -- -- 200 --
Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write/Read rise/fall time Setup time (RS to CS*,WR*, RD*) Address hold time VLD setup time VLD hold time Write data set up time Write data hold time Read data delay time Read data hold time
tWRr, WRf ns tAS tAH tVS tVH tDSW tH tDDR tDHR ns ns ns ns ns ns ns ns
High-speed Write mode (HWM1-0 = 11) (Vcc = 2.2V to 3.3V during operation)
Item Bus cycle time Write Read Symbol Unit tCYCW tCYCR PWLW PWLR PWHW PWHR ns ns ns ns ns ns Test Condition Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 Min 90 500 35 250 45 200 -- 20 20 20 10 35 20 -- 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- 25 -- -- -- -- -- -- 200 --
Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write/Read rise/fall time Setup time (RS to CS*,WR*, RD*) Address hold time VLD setup time VLD hold time Write data set up time Write data hold time Read data delay time Read data hold time
tWRr, WRf ns tAS tAH tVS tVH tDSW tH tDDR tDHR ns ns ns ns ns ns ns ns
Rev.1.11, Oct. 02.2003, page 159 of 175
HD66776 Clock Synchronized Serial Interface Timing Characteristics Vcc = 2.2V to 3.3V
Item Write (received) Serial clock cycle time Read (transmitted) Serial clock high-level pulse width Write (received) Read (transmitted) Serial clock low-level pulse width Write (received) Read (transmitted) Serial clock rise/fall time Chip select set up time Chip select hold time Serial input data set up time Serial input data hold time Serial output data delay time Serial output data hold time tscr, tscf tCSU tCH tSISU tSIH tSOD tSOH ns ns ns ns ns ns ns Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 Figure 2 -- 20 60 30 30 -- 5 -- -- -- -- -- -- -- 20 -- -- -- -- 130 -- tSCL tSCL ns ns Figure 2 Figure 2 40 150 -- -- -- -- tSCH tSCH ns ns Figure 2 Figure 2 40 150 -- -- -- -- Symbol Unit tSCYC tSCYC s s Test Condition Figure 2 Figure 2 Min 0.1 0.35 Typ -- -- Max 20 20
Reset Timing Characteristics (Vcc = 2.2 to 3.3V)
Item Reset low-level width Reset rising time Symbol tRES trRES Unit ms s Test Condition Figure 3 Figure 3 Min 1 -- Typ -- -- Max -- 10
Rev.1.11, Oct. 02.2003, page 160 of 175
HD66776 RGB interface timing characteristic 18/16 bit RGB interface (HWM1-0 =11), Vcc = 2.2V to 3.13V
Item VSYNC/HSYNC Set up time ENABLE Set up time ENABLE Hold time VLD Set up time VLD Hold time DOTCLK "Low" Level pulse width DOTCLK "High" Level pulse width DOTCLK cycle time Data Set up time Data Hole time DOTCLK, VSYNC, HSYNC rising and falling time Symbol tSYNCS tENS tENH tVLS tVLH PWDL PWDH tCYCD tPDS tPDH trgbr, trgbf Unit clock ns ns ns ns ns ns ns ns ns ns Test Condition Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 min. 10ns 25 40 25 40 40 40 100 25 40 typ. max. 1 25
6 bit RGB interface (HWM1-0 = 11), Vcc = 2.2V to 3.3 V
Item VSYNC/HSYNC Set up time ENABLE Set up time ENABLE Hold time VLD Set up time VLD Hold time DOTCLK "Low" Level pulse width DOTCLK "High" Level pulse width DOTCLK cycle time Data Set up time Data Hole time DOTCLK, VSYNC, HSYNC rising and falling time Symbol tSYNCS tENS tENH tVLS tVLH PWDL PWDH tCYCD tPDS tPDH trgbr, trgbf Unit clock ns ns ns ns ns ns ns ns ns ns Test Condition Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 Min. 10ns 20 23 20 23 25 25 55 20 23 typ. max. 1 25
Rev.1.11, Oct. 02.2003, page 161 of 175
HD66776 LCD driver output characteristic
Item Symbol Unit Test Condition Vcc = 3V, VLCD = 5.5V, VDH = 5.0V R-C Oscillation; fOSC = 370kHz(320 line) Ta = 25 C, REV = "0", SAP = "001" VRP14-00 = "0", PKP52-00 = "0", PRP12-00 = "0" VRN14-00 = "0" PKN52-00 = "0", PRN12-00 = "0" All pins change at the same time from same grayscale. The time till output level reaches 35mV when VCOM polarity changes. Load resistance R = 10k, Load capacity C = 20pF Min. Typ. Max Note
Delay time of output driver
tdd
s
30
(10)
Rev.1.11, Oct. 02.2003, page 162 of 175
HD66776
Electrical Characteristics notes
1. For bare die and wafer products, specified up to 85C. 2. The following three circuits are I pin, i/O pin configuration
Pins: RESET*, CS*, WR*/SCL, RD, RS, VLD, IM2-1, IM0/ID, TEST, VDDTEST, VSYNC, HSYNC, DOTCLK, ENABLE, PD17-0 Vcc Pins: OSC2-3, RESET01, RESET02, FLM, M, DISPTMG, CLA, CLB, CLC, SFTCLK1-2, GCL, GDA, GCS*, EQ, DCCLK
Vcc PMOS NMOS PMOS
NMOS GND
GND
Pins: DB17 -DB2, DB1/SD0, DB0/SD1 Vcc
PMOS
(Input circuit)
NMOS Vcc PMOS
(Tri-state output circuit)
Output enable Output data
NMOS GND
3. The TEST and VDDTEST pin must be grounded and the IM2/1 and IM0/ID pins must be grounded or connected to Vcc. 4. This excludes the current flowing through output drive MOSs. 5. This excludes the current flowing through the input/output units. The input level must be fixed high or low because through current increases if the CMOS input is left floating. Even if the CS pin in low or high when an access with the interface pin is not performed, current consumption does not change.
Rev.1.11, Oct. 02.2003, page 163 of 175
HD66776 6. The following shows the relationship between the operation frequency (fosc) and current consumption (Icc).
Vcc = 3V Reference data Vcc = 3V Reference data
typ.
100
ICI op ( A)
lop ( A)
150
150 100
typ.
50 0 500 600 100 200 300 400 R-C Oscillation frequency: fOSC (kHz)
50 0 500 600 100 200 300 400 R-C Oscillation frequency: fOSC (kHz)
Vcc = 3V, DDVDH = 5,5V Reference data
ILCD ( A)
750 700 650 600 550 500 0 4.0 4.5 5.0
typ.
VDH (V)
7. Indicates the output voltage difference between the pins next to in the same display. Output voltage deviation is the reverence value. 8. Fluctuation of average output voltage is the deviation of average output voltage between chips. Average output voltage is the average voltage of all pins in one chip.
Rev.1.11, Oct. 02.2003, page 164 of 175
HD66776 9. Applies to the internal oscillator operations using external oscillation resistor Rf.
OSC1 Rf OSC2
Since the oscillation frequency varies depending on the OSC1 and OSC2 pin capacitance, the wiring length to these pins should be minimized.
Oscillation frequency
fOSC (kHz)
25oC Reference data Rf=90k
700 600 Rf=110k 500 Rf=130k 400 300 200 100 2.2 2.4 2.6 2.8 3.0 3.2 Power supply voltage Vcc (V) Rf=150k Rf=180k Rf=250k Rf=220k Rf=300k Rf=400k
10. Supplies to the internal oscillator operations using external oscillation resistor Rf.
LCD Driver output delay time tDD ( s)
Reference data
Oscillation frequency
30
typ.
20
10
Vcc = 3V, VLCD = 5.5V, VDH = 5.0V, RC Oscillation, fosc = 370kHz (320lines) Ta = 25oC, REV = "0", SAP = "001", PKP52-00 = "0", PRP12-00 = "0", VRP14-00 = "0", PKN52-00 = "0", PRN12-00 = "0", VRN14-00 = "0", All pins change at the same time from the same grayscale. The time till output level reaches: 35+/-mV when VCOM polarity changes Load resistance R = 10k/1pin
10
20
Load Capacity C(pF)
AC characteristic measuring load circuit Data bus: DB17-DB0, PD17-0 Test Point 50pF
LCD driver output characteristic measuring load circuit LCD output: S1- S256 Test Point Load Resistance R 10k Load Capacity C
20pF
Rev.1.11, Oct. 02.2003, page 165 of 175
HD66776
80-system Bus Operation
RS
VIH VIL tAS VIH
VIH VIL tAH
CS*
VIL
Note 1)
PWLW, PWLR WR*
PWHW, PWHR
VIH
VIL
RD*
VIH VIL tWRf
tWRr
tCYCW, tCYCR
tVS
tVH
VIH VIL
VLD
VIH VIL
tDSW
Note2
tH Wrire data VIH VIL
tDHR
DB0 to DB17
tDDR
VIH VIL
Note2
DB0 to DB17
VOH1 VOL1
Read data
VOH1 VOL1
Note1: Unused DB pins while bus interface must be fixed to "Vcc" or "GND" level.
Figure 1
Rev.1.11, Oct. 02.2003, page 166 of 175
HD66776
Clock Synchronized Serial Interface Operation
Start: S
CS* VIL
End: P
VIH
VIL
tSCYC tscf
tCSU SCL
tscr tSCH
tSCL
tCH
VIH VIL
VIL
VIH VIH VIL
tSIH
VIH
VIL
tSISU
SDI
VIH
VIL
tSOD
Input data
VIH
VIL
Input data
tSOH
SDO
VOH1 VOL1
Output data Output data VOH1 VOL1
Figure 2
Reset Operation
trRES VIL VIL VIL
tRES RESET*
Figure 3
Rev.1.11, Oct. 02.2003, page 167 of 175
HD66776
RGB I/F Operation
trgf b trgr b VIH
VIL VIH VIL
tSYNCS
VSYNC HSYNC
tEN S ENBLE A
VIH VIL VIH VIL
tEN H
VIH VIL VIH VIL
tVLS VLD
VIH VIL VIH VIL
tVLH
VIH VIL VIH VIL
trgf b
PWDL
trgf b
PWDH VIH VIL
DOT LK C
VIH VIL
VIL tCYCD
VIH
tPDS PD17 0 VIH VIL VIH VIL
tPDH Write Data
VIH VIL VIH VIL
Figure 4
LCD Driver Output Character
VCOM tDD
Certain grayscale voltage 35mV
S1-256
Certain grayscale voltage 35mV
Figure 5
Rev.1.11, Oct. 02.2003, page 168 of 175
HD66776
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
http://www.renesas.com
Copyright (c) 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.
Colophon 0.0
Rev.1.11, Oct. 02.2003, page 169 of 175
HD66776
Revision Record
Rev 0.0 0.1 Date 2002.6.21 2002.9.27 All page 2 3 Page Contents First edition Change the number of source channel from "240" to "256" Capacity of internal RAM from "172,800" to "184,320". Add "RESET01" and "RESET02" pins to Figure 1. Change "VDD" to "VDD1" and "VDDOUT" to "VDD2" in Figure 1. Change capacity of Graphic RAM form "172,800" to "184,320" in Figure 1. Delete "PMON" in Figure 1. 4 5 Add items to the table in VLD Functions. Add a new function explanation sentence to the ENABLE. Add items to the table in ENABLE Functions. 6 Change function explanation sentence of VSYNC. Add a table in VSYNC Functions. Change function explanation sentence of HSYNC. Add a table in HSYNC Functions. Change function explanation sentence of DOTCLK. Add a table in DTCLK Functions. Change "FLM" to "FLM1,2". Change "SFTCLK1" to "SFTCLK11, SFTCLK12". Change "SFTCLK2" to "SFTCLK21, SFTCLK22". Change "CLA" to "CLA1, CLA2". Change "CLB" to "CLB1, CLB2". Change "CLC" to "CLC1, CLC2". Change "DISPTMG "to "DISPTMG1, DISPTMG2". Change "M" to "M1, M2". 7 Change "EQ" to "EQ1, EQ2". Change "DCCLK" to "DCCLK1, DCCLK2". Change "GCL" to "GCL1, GCL2". Change "GDA" to "GDA1, GDA2. Change "GCS*" to "GCS*1, GCS*2". Change DDVDH from "4.5V to +5.5V" to "4.0V to +5.5V". Add a row of "AGND" after "Vcc, GND". Change "RESET1*, RESET*2" to "RESET1*". Add a row of "RESET01, RESET02" after "RESET1*". 8 Change "VDD" to "VDD1".
Rev.1.11, Oct. 02.2003, page 170 of 175
HD66776
Rev 0.1 Date 2002.9.27 Page 8 Contents Change function explanation sentence of "VDD1". Add a row of "VDD2" after "VDD1" 9 10,11,12 13 14 17 18,19,22, 23, 24 21 27 30 Add a new page "HD667B768 PAD Arrangement". Add new pages. "HD667B76 PAD Coordinate". Add a new page "Bump Arrangement" Add rows and columns to the Table 4. (VPL) Change contents of S255 and S256 in Table 6. Change "Note" from "n = lower eight bit of address (239 to 0)" to "n = ...(0 to 255)". Change contents of Table 6. Ex. "000EF"H to "000FF"H Figure 31: Change pins of IB10 to 5. From "ID7, ID6, ID5, 0,0,0" to "ID10, ID9, ID8, ID7, ID6, ID5". Figure 36: Change pins of IB15 and 14. From "0,0" to "TRI, DFM". Change number in Figure 37. From "13FEFFh" to "13FFFh" 32 36 40 41 57 58 59 62 70 71 74 75 81 Add a new page. Change a bit of DB12 from "0" to "CAD" in Figure 46. Add rows to the Table 20. Change "Number of Clock for 1 period" of Table 22. From "16" to "8.0", "17" to "8.5", and "18" to "9.0". Change DCCLK operation frequency in Table 51. From "2" to "4", "4" to "8", "8" to "16", and "16" to "32". Delete Power control (3) (R102h) in rev. 0.0, and move up the numbers of Power controls. (From "4" to "3", "5" to "4", and "6" to "5".) Change "E" to "F" in Table 52. (Ex. From "000EF"H" to "000FF"H".) Add a new page. Change "R204h" to "R203h", and "R205h" to "R204h". Change "0" to "VRP14", and "VRN04" to "0". Change "EF" to "FF"in a explanation sentence of "HSA7-0/HEA7-0" and Figure 92. Change "102h". (From "Power control (2)" to "Setting inhibited".) Add explanation sentence of 80-system 8-bit bus interface. ("According to the setting of TRI, RAM data for one word are divided into two ot three for two time transfer or three time transfer.") Add a new page. Change RAM write speed from "5.70MHz" to "6.08MHz. Change the time of RAM write from "76800" to "81920". 90 102 104 105 Change Ram write speed from "5.70MHz" to "6.08MHz". Delete "R202" from the Index in Figure 134. Add a sentence, "Can be set by word unit", to the explanation o f Window address of High-Speed RAM Write. Change "HSA1-0= "10, HEA1-0= "00" to "HSA7-0, HEA7-0".
82 89
Rev.1.11, Oct. 02.2003, page 171 of 175
HD66776
Rev 0.1 Date 2002.9.27 Page 105 106 107 124 Non 126 Non 127 Contents Change "h13FEF" to "h13FFF" in Figure 136. Change "EF" to "FF" in Figure 137. Delete the cells of LG2-0 in Table 66. Add a new page. Delete a page of indicating a flow of switching display mode. Revise the Figure 158. Delete a page of Cadd mode. Change "Cst mode 1" to "Mode 1" Delete "(1) CAD = 0: Cst mode" Delete (*5). 128 129 Revise Figure 159. Change "Cst mode 2" to "Mode 2". Delete (1) CAD = 0: Cst mode" Delete (*5). 130 131 134 141 146-158 0.21 2002.10.17 127 Revise Figure 160. Revise the Figure 161. Revise the Figure 164. Change "241" to "321", "242" to "322", and "256" to "336" in Figure 171. Add new pages. Delete p127 to 130 in revision 0.1 and insert a new p127 "Example of chipset connection". Clearly indicated the Note "Vcc and Vci" and "AGND and GND" must be connected on FPC". Correct "HD667P10" to "667P20" Functions of "RS": Correct "Low: Index/status" to "Low :Index". Functions of "WR*/SCL": Correct "Data is written on ..." to "Data is read...". Functions of "V0p, V63P: Correct "(SAP2-0= "001", "010", "001"..." to "(SAPO2-0 = "001", "010", "011"...)". Delete the row of "VDDOUT". 18 21 25 29 Delete "conventional" from the description of External Display Interface (RGB-I/F, VSTNC-I/F). Correct the title of Figure 10 from "80-system 8-bit interface/SPI" to "80-system 8-bit interface (1)". Correct the title of Figure 20 from "80-system 8-bit interface/SPI" to "80-system 8-bit interface (1)". Correct the title of Figure 30 from "80-System 8-Bit Interface (SPI two transfers/pixel)" to "80-System 8-Bit Interface/ SPI (two transfers/pixel)". Description of "HWM1-0": Correct "When HWM=1..." to "When HWM=11...".
0.3
2002.11.21
all 7 8 11
33
Rev.1.11, Oct. 02.2003, page 172 of 175
HD66776
Rev 0.3 Date 2002.11.21 Page 33 Contents Description of "AM": Correct the second sentence. "the data is continuously written in parallel" to "the data is continuously written horizontally". Add Figure 41. Correct "HD66772" to "HD66776" in the description of "IDX2-0". Correct Figure 46. 43 43 Formula for the frame frequency: Correct "Clock cycles per raster-row" from "RTN bit" to "RTNI bit". Table 22: Correct "Number of Clock for 1 period" as below. Error 8.0 clock 8.5 clock 9.0 clock 127.0 clock 127.5 clock 58 59 Correct 16 clock 17 clock 18 clock 254 clock 255 clock
35 39
Correct Table 48. Delete "gate driver" from the description of "SLP". Change "gate driver" to "power supply IC" in the description of "STB".
61
Add "Power Control 6 (105h)" in title and in Figure 67. Add the description of "VGH4-0" and "VGL4-0". Add "VREG2OUT" in the description of "VRL2". Correct the description of "PON "from "Operation start bit for the stepup 3 circuit" to "Set operation/stop of VLOUT3.". Add "VGH4-0" and "VGL4-0" in the Note.
78 79 97
Correct Table 57 Instruction list. Delete "gate driver" from the description of "Reset Function". Delete sentences from the description of "VLD and ENABLE signal". (Deleted sentences: "When ENABLE is active, the address is not updated. When VLD is active and ENABLE is active, the address is updated. ENABLE must be set to "L".) Correct "VSYNC" to "RGB" in the description on Note in Figure 121. Correct "clock" to "pixel" in Note1, and "VSYNC" to "RGB" in Note 3. Correct "MIF1-0 = pins to "01" to "RIM1-0 = "00"" in the description of 18-bit RGB interface. Add "6-bit RGB interface" to the description of "Usage on external display interface d)". Correct "PD17-0" to "PD17-12" in the description of "Usage on external display interface d).
98 99 101 102
106 107 109
Correct the waveform of Figure 134. (Upside down) Correct the waveform of Figure 135. (Upside down) Correct "(HS71 to 0,)" to "(HAS 7 to 0) in the description of "HighSpeed RAM Write in the Window in the Waveform Address.
Rev.1.11, Oct. 02.2003, page 173 of 175
HD66776
Rev 0.3 Date 2002.11.21 Page 109 113 114 125 135 141 145 Contents Correct "AD = h00810" in the flow to "AD = h00812" in the flow. Correct "WM17-0 = "007FF"H" to "WM17-0 = "00FFF" in Figure 140. Correct "WM17-0 = "007FF"H" to "WM17-0 = "00FFF" in Figure 141. Correct "262,114" to "262,144" in Table 77. Correct "t1:20ns" to "t1:45ns" and "t2: 20ms" to t2: 25ns" in Figure164. Delete "on the master side" from Note in Figure 170. Change "(R14) to (R402, R403)" and "(R15)" to "(R404, R405)" in the st nd description of "Restrictions on 1 /2 Screen Driving Position register Settings". Change "In all other display area refers to the output level based on the PT setting. (non-display)" to "RAM data in other areas are not displayed." Correct "SE27" to "SE28", "SS27" to "SS28", "SE17" to "SE18" and "SS17" to "SS18" in Table 80. 149,150 153 154 155 158 159 1.01 2003.3.5 5 Correct numbers in Min of Table 84, 85,86, and 87. Correct numbers in Min of Table 93. Correct "Pins: DB15-DB2..." to "Pins: DB17-DB2..." in Figure 176. Correct Note 4, 5, 6, 7, and 8. Add "trRES" to Figure 186. Correct "S1-528" to "S1 to 256" in Figure 188. Correct power supply voltage. From "Vcc = 1.7 to 3.3V" to "Vcc = 2.2 to 3.3V". From "DDVDH = 4.0 to 5.5V" to "DDVDH = "4.0 to 5.9V". Correct Block diagram Correct Function of DDVDH. From "4.0 V to +5.5V" to "4.0V to 5.9V" Correct Function of VDH. From HD667P20" to "HD667P21". Correct Function of Vcc, GND. From "+1.7V to +3.3V" to "2.2V to +3.3V". Correct Function of DUMMY pin. 17 18 Add a new page. "Pin connecting resistance recommended value" Correct the first sentence of System interface explanation. From "The HD66776 has four high-speed,,,," to " The HD66776 has five highspeed,,,,," Correct explanation of FP3-0/BP3-0. Add "Instruction for setting FP.BP" 40 47 64 81 138 141 161-163 Correct tabel"HD667P20 Instruction chart" Correct "DIVE1-0". Add "LRL3". Correct "VCOMG" , "VDV4-0", and "VRL2". Add "VRL3(0)" to the Instruction chart. Correct "Power supply On" setting flow. Correct "Deep stand-by" setting flow. Correct "Electrical characteristic".
6 10
39
Rev.1.11, Oct. 02.2003, page 174 of 175
HD66776
Rev 1.10 Date 2003.7.15 Page 43 66 1.11 200.10.2 33 Contents Delete "Dk1" from the table of HD667P20 instruction Correct description of VRL3-0 bits. Error correction. Driver Output Control register
Rev.1.11, Oct. 02.2003, page 175 of 175

▲Up To Search▲

Price & Availability of HD66776

	To Download HD66776 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .